MC9S08DZ60ACLF Freescale Semiconductor, MC9S08DZ60ACLF Datasheet - Page 402

• Manufacturer Part Number: MC9S08DZ60ACLF
• Description: IC MCU 60K FLASH 4K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ60ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• For Use With: DEMO9S08DZ60 - BOARD DEMOEVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 18 Debug Module (S08DBGV3) (128K)
18.3.3.9
1
402
end-run
Module Base + 0x0008
end-run
or non-
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
PAGSEL
RWAEN
Reset
Bit 16
Field
RWA
POR
7
6
5
0
W
R
1
RWAEN
Read/Write Comparator A Enable Bit — The RWAEN bit controls whether read or write comparison is enabled
for Comparator A.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Read/Write Comparator A Value Bit — The RWA bit controls whether read or write is used in compare for
Comparator A. The RWA bit is not used if RWAEN = 0.
0 Write cycle will be matched
1 Read cycle will be matched
Comparator A Page Select Bit — This PAGSEL bit controls whether Comparator A will be qualified with the
internal signal (mmu_ppage_sel) that indicates an extended access through the PPAGE mechanism. When
mmu_ppage_sel = 1, the 17-bit core address is a paged program access, and the 17-bit core address is made
up of PPAGE[2:0]:addr[13:0]. When mmu_ppage_sel = 0, the 17-bit core address is either a 16-bit CPU address
with a leading 0 in bit 16, or a 17-bit linear address pointer value.
0 Match qualified by mmu_ppage_sel = 0 so address bits [16:0] correspond to a 17-bit CPU address with a
1 Match qualified by mmu_ppage_sel = 1 so address bits [16:0] compare to flash memory address made up of
Comparator A Extended Address Bit 16 Compare Bit — The Comparator A bit 16 compare bit controls
whether Comparator A will compare the core address bus bit 16 to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Debug Comparator A Extension Register (DBGCAX)
U
0
7
leading zero at bit 16, or a 17-bit linear address pointer address
PPAGE[2:0]:addr[13:0]
Figure 18-10. Debug Comparator A Extension Register (DBGCAX)
= Unimplemented or Reserved
RWA
U
0
6
Table 18-11. DBGCAX Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
PAGSEL
U
0
5
0
0
0
4
Description
0
0
0
3
0
0
0
2
Freescale Semiconductor
0
0
0
1
Bit 16
U
0
0