MC908GR60ACFAE Freescale Semiconductor, MC908GR60ACFAE Datasheet - Page 148

• Manufacturer Part Number: MC908GR60ACFAE
• Description: IC MCU 60K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR60ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Input/Output (I/O) Ports
T2CH5–T2CH2 — Timer 2 Channel I/O Bits
12.8.2 Data Direction Register F
Data direction register F (DDRF) determines whether each port F pin is an input or an output. Writing a 1
to a DDRF bit enables the output buffer for the corresponding port F pin; a 0 disables the output buffer.
DDRF7–DDRF0 — Data Direction Register F Bits
Figure 12-22
When bit DDRFx is a 1, reading address $0440 reads the PTFx data latch. When bit DDRFx is a 0,
reading address $0440 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
148
The PTF7/T2CH5–PTF4/T2CH2 pins are the TIM2 input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTF7/T2CH5–PTF4/T2CH2 pins are timer channel
I/O pins or general-purpose I/O pins. See
Timer Interface Module
These read/write bits control port F data direction. Reset clears DDRF7–DDRF0, configuring all port F
pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
shows the port F I/O logic.
Address:
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
READ DDRF ($0444)
WRITE DDRF ($0444)
WRITE PTF ($0440)
READ PTD ($0440)
DDRF7
$0444
Bit 7
0
(TIM2).
Figure 12-21. Data Direction Register F (DDRF)
DDRF6
6
0
RESET
Figure 12-22. Port F I/O Circuit
DDRF5
5
0
Chapter 17 Timer Interface Module (TIM1)
Table 12-7
NOTE
DDRF4
DDRFx
PTFx
4
0
summarizes the operation of the port F pins.
DDRF3
3
0
DDRF2
2
0
DDRF1
1
0
Freescale Semiconductor
DDRF0
Bit 0
PTFx
0
and
Chapter 18