MC908GR60ACFAE Freescale Semiconductor, MC908GR60ACFAE Datasheet - Page 35

• Manufacturer Part Number: MC908GR60ACFAE
• Description: IC MCU 60K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR60ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
$003A
$003B
$0036
$0037
$0038
$0039
Addr.
$0030
$0031
$0032
$0033
$0034
$0035
TIM2 Channel 0 Status and
TIM2 Channel 1 Status and
PLL Multiplier Select High
Control Register (T2SC0)
Control Register (T2SC1)
PLL Multiplier Select Low
Register High (T2CH0H)
Register High (T2CH1H)
PLL VCO Select Range
Register Low (T2CH0L)
Register Low (T2CH1L)
PLL Bandwidth Control
Register Name
PLL Control Register
Register (PBWC)
Register (PMSH)
Register (PMRS)
Register (PMSL)
TIM2 Channel 0
TIM2 Channel 0
TIM2 Channel 1
TIM2 Channel 1
See page 237.
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See page 240.
See page 237.
See page 240.
See page 240.
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
See page 81.
See page 82.
See page 83.
See page 84.
See page 84.
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9)
Reserved
(PCTL)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
PLLIE
AUTO
CH0F
Bit 15
CH1F
Bit 15
MUL7
VRS7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
CH0IE
CH1IE
LOCK
MUL6
VRS6
PLLF
14
14
6
0
6
0
6
0
0
0
0
1
1
0
0
PLLON
MS0B
MUL5
VRS5
ACQ
13
13
5
0
5
0
0
5
1
0
0
0
0
0
0
0
R = Reserved
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
MS1A
MS0A
MUL4
VRS4
BCS
12
12
4
0
4
0
4
0
0
0
0
0
0
0
0
0
MUL11
ELS0B
ELS1B
MUL3
VRS3
11
11
R
U
R
3
0
3
0
3
0
0
0
0
0
0
U = Unaffected
MUL10
ELS0A
ELS1A
MUL2
VRS2
10
10
Input/Output (I/O) Section
R
U
R
2
0
2
0
2
0
0
0
0
0
0
TOV1
MUL9
MUL1
TOV0
VPR1
VRS1
U
R
1
0
9
1
0
9
1
0
0
0
0
0
0
CH0MAX
CH1MAX
VPR0
MUL8
MUL0
VRS0
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
R
U
R
0
0
0
0
0
0
1
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