MC908GR60ACFAE Freescale Semiconductor, MC908GR60ACFAE Datasheet - Page 91

• Manufacturer Part Number: MC908GR60ACFAE
• Description: IC MCU 60K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR60ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

COPRS — COP Rate Select Bit
LVISTOP — LVI Enable in Stop Mode Bit
LVIRSTD — LVI Reset Disable Bit
LVIPWRD — LVI Power Disable Bit
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
SSREC — Short Stop Recovery Bit
Freescale Semiconductor
COPRS selects the COP timeout period. Reset clears COPRS. See
Properly (COP) Module
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
LVIRSTD disables the reset signal from the LVI module. See
LVIPWRD disables the LVI module. See
LVI5OR3 selects the voltage operating mode of the LVI module (see
(LVI)). The voltage mode selected for the LVI should match the operating V
Electrical
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay.
1 = COP timeout period = 8176 CGMXCLK cycles
0 = COP timeout period = 262,128 CGMXCLK cycles
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
1 = LVI module resets disabled
0 = LVI module resets enabled
1 = LVI module power disabled
0 = LVI module power enabled
1 = LVI operates in 5-V mode
0 = LVI operates in 3-V mode
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
Note: LVI5OR3 is only reset via POR (power-on reset).
Specifications) for the LVI’s voltage trip points for each of the modes.
Address:
The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
Exiting stop mode by any reset will result in the long stop recovery.
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
COPRS
$001F
Bit 7
0
Figure 5-2. Configuration Register 1 (CONFIG1)
LVISTOP
6
0
LVIRSTD
5
0
Chapter 11 Low-Voltage Inhibit
LVIPWRD
NOTE
NOTE
4
0
LVI5OR3
See note
3
Chapter 11 Low-Voltage Inhibit
SSREC
2
0
Chapter 6 Computer Operating
Chapter 11 Low-Voltage Inhibit
(LVI).
STOP
1
0
DD
(see
Functional Description
COPD
Bit 0
Chapter 20
0
(LVI).
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