MC9S12C128CFUE Freescale Semiconductor, MC9S12C128CFUE Datasheet - Page 62

IC MCU 128K FLASH 25MHZ 80-QFP

MC9S12C128CFUE

Manufacturer Part Number
MC9S12C128CFUE
Description
IC MCU 128K FLASH 25MHZ 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12C128CFUE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/SCI/SPI
Total Internal Ram Size
4KB
# I/os (max)
60
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/2.97V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4000 B
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
61
Number Of Timers
1
Operating Supply Voltage
- 0.3 V to + 6.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.6.2
Resets are a subset of the interrupts featured in
system reset are summarized in
changed to known start-up states. Refer to the respective module Block User Guides for register reset
states.
1.6.2.1
1.6.2.2
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states. Refer to the HCS12 Multiplexed External
Bus Interface (MEBI) Block Guide for mode dependent pin configuration of port A, B and E out of reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
Refer to
after reset.
The RAM array is not automatically initialized out of reset.
1.7
1.7.1
External paging is not supported on these devices. In order to access the 16K flash blocks in the address
range 0x8000–0xBFFF the PPAGE register must be loaded with the corresponding value for this range.
Refer to
For all devices Flash Page 3F is visible in the 0xC000–0xFFFF range if ROMON is set. For all devices
(except MC9S12GC16) Page 3E is also visible in the 0x4000–0x7FFF range if ROMHM is cleared and
ROMON is set. For all devices apart from MC9S12C32 Flash Page 3D is visible in the 0x0000–0x3FFF
range if ROMON is set...
62
Figure 1-2
Table 1-11
Device Specific Information and Module Dependencies
Resets
PPAGE
COP Watchdog Reset
Reset Summary Table
Effects of Reset
Clock Monitor Reset
Low Voltage Reset
For devices assembled in 48-pin or 52-pin LQFP packages all non-bonded
out pins should be configured as outputs after reset in order to avoid current
drawn from floating inputs. Refer to
Power-on Reset
External Reset
to
Reset
for device specific page mapping.
Figure 1-6
Table
footnotes for locations of the memories depending on the operating mode
MC9S12C-Family / MC9S12GC-Family
1-10. When a reset occurs, MCU registers and control bits are
Table 1-10. Reset Summary
Priority
1
1
1
2
3
Table
Rev 01.24
NOTE
Table 1-5
1-9. The different sources capable of generating a
VREG module
CRG module
CRG module
CRG module
RESET pin
Source
for affected pins.
0xFFFC, 0xFFFD
0xFFFE, 0xFFFF
0xFFFE, 0xFFFF
0xFFFE, 0xFFFF
0xFFFA, 0xFFFB
Freescale Semiconductor
Vector

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