MC9S12E256MFUE Freescale Semiconductor, MC9S12E256MFUE Datasheet - Page 303

• Manufacturer Part Number: MC9S12E256MFUE
• Description: IC MCU 256K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256MFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 60
• Ram Memory Size: 16KB
• Cpu Speed: 25MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.3.2.2
Read and write anytime
Freescale Semiconductor
IBC[7:0]
Reset
Field
7:0
W
R
IBC7
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in
IIC Frequency Divider Register (IBFD)
0
7
Table
10-4.
IBC5-3
(bin)
000
001
010
011
100
101
110
111
IBC6
Figure 10-3. IIC Bus Frequency Divider Register (IBFD)
= Unimplemented or Reserved
0
6
Table 10-4. I-Bus Tap and Prescale Values
scl2start
(clocks)
IBC2-0
Table 10-3. IBFD Field Descriptions
(bin)
000
001
010
011
100
101
110
111
126
14
30
62
IBC5
2
2
2
6
MC9S12E128 Data Sheet, Rev. 1.07
0
5
IBC4
scl2stop
SCL Tap
(clocks)
(clocks)
0
4
129
10
12
15
17
33
65
5
6
7
8
9
7
7
9
9
Description
IBC3
0
3
SDA Tap
(clocks)
(clocks)
scl2tap
126
14
30
62
1
1
2
2
3
3
4
4
4
4
6
6
Chapter 10 Inter-Integrated Circuit (IICV2)
IBC2
0
2
(clocks)
tap2tap
128
16
32
64
1
2
4
8
IBC1
0
1
IBC0
0
0
303