MC9S12E256MFUE Freescale Semiconductor, MC9S12E256MFUE Datasheet - Page 321

• Manufacturer Part Number: MC9S12E256MFUE
• Description: IC MCU 256K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256MFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 60
• Ram Memory Size: 16KB
• Cpu Speed: 25MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Dummy Read
From IBDR
Switch To
Rx Mode
Y
Byte To IBDR
(Master Rx)
Transmitted
Addr Cycle
Write Next
Last Byte
RXAK=0
End Of
?
?
?
Y
N
N
TX
Stop Signal
Generate
Figure 10-11. Flow-Chart of Typical IIC Interrupt Routine
Y
N
Tx/Rx
Set TXAK =1
?
Y
Byte To Be Read
Byte To Be Read
From IBDR
MC9S12E128 Data Sheet, Rev. 1.07
Read Data
And Store
2nd Last
RX
Last
?
?
N
N
Stop Signal
Generate
Y
Y
RTI
Master
Mode
Clear
IBIF
?
Write Data
To IBDR
(Read)
Set TX
Mode
N
N
Y
Dummy Read
From IBDR
Clear IBAL
IAAS=1
Set RX
SRW=1
Mode
Y
?
?
Chapter 10 Inter-Integrated Circuit (IICV2)
N
Address Transfer
(Write)
Tx Next
Byte
Y
Y
Y
Dummy Read
From IBDR
Arbitration
ACK From
Switch To
Receiver
IAAS=1
Rx Mode
TX/RX
Lost
?
?
?
?
N
N
N
TX
Data Transfer
From IBDR
Read Data
And Store
RX
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