MC9S12E256MFUE Freescale Semiconductor, MC9S12E256MFUE Datasheet
MC9S12E256MFUE
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MC9S12E256 Data Sheet HCS12 Microcontrollers MC9S12E256 Rev. 1.08 01/2006 freescale.com ...
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MC9S12E256 Data Sheet MC9S12E256 Rev. 1.08 01/2006 ...
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... Date Level November 10, 2005 1.07 January 18, 2005 1.08 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2006. All rights reserved. 4 Description New Data Sheet Table A-4. Operating Conditions — ...
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... Background Debug Module (BDMV4 445 Chapter 16 Debug Module (DBGV1 469 Chapter 17 Interrupt (INTV1 501 Chapter 18 Multiplexed External Bus Interface (MEBIV3 509 Chapter 19 Module Mapping Control (MMCV4 541 Appendix A Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 Appendix B Ordering Information and Mechanical Drawings 594 Freescale Semiconductor MC9S12E256 Data Sheet, Rev. 1.08 5 ...
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... List of Chapters 6 MC9S12E256 Data Sheet, Rev. 1.08 Freescale Semiconductor ...
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... PM6 / SDA — Port M I/O Pin 1.4.22 PM5 / TXD2 — Port M I/O Pin 1.4.23 PM4 / RXD2 — Port M I/O Pin 1.4.24 PM3 — Port M I/O Pin 1.4.25 PM1 / DAO1 — Port M I/O Pin Freescale Semiconductor Contents Title Chapter 1 MC9S12E256 Data Sheet, Rev. 1.08 ...
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... Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 1.8 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.8.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.8.2 Pseudo Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.8.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.8.4 Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.9 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.9.1 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.9.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.10 Recommended Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8 Title MC9S12E256 Data Sheet, Rev. 1.08 Page Freescale Semiconductor ...
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... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 3.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.3.1 Port 130 3.3.2 Port 136 3.3.3 Port 141 3.3.4 Port 144 3.3.5 Port 147 3.3.6 Port 151 3.3.7 Port 154 Freescale Semiconductor Title Chapter 2 Chapter 3 MC9S12E256 Data Sheet, Rev. 1.08 Contents Page 9 ...
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... Real-Time Interrupt (RTI 187 4.4.7 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 4.4.8 Low-Power Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.4.9 Low-Power Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.4.10 Low-Power Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 10 Title Chapter 4 — PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . . . . 167 MC9S12E256 Data Sheet, Rev. 1.08 Page Freescale Semiconductor ...
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... Analog Circuitry Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . 207 DDA SSA 6.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Freescale Semiconductor Title Chapter 5 Oscillator (OSCV2) — PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . 202 Chapter 6 MC9S12E256 Data Sheet, Rev. 1.08 ...
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... TXD — SCI Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 8.2.2 RXD — SCI Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 8.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 12 Title Chapter 7 Chapter 8 MC9S12E256 Data Sheet, Rev. 1.08 Page Freescale Semiconductor ...
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... Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 9.4.8 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 9.4.9 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 9.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 9.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 9.6.1 MODF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 9.6.2 SPIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 9.6.3 SPTEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Freescale Semiconductor Title Chapter 9 MC9S12E256 Data Sheet, Rev. 1.08 Contents Page 13 ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 11.4.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 11.4.2 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 11.4.3 PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 11.4.4 Independent or Complementary Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 11.4.5 Deadtime Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 11.4.6 Software Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 14 Title Chapter 10 Inter-Integrated Circuit (IICV2) Chapter 11 MC9S12E256 Data Sheet, Rev. 1.08 Page Freescale Semiconductor ...
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... IOC5 — Input Capture and Output Compare Channel 5 Pin . . . . . . . . . . . . . . . . . . . . 414 13.2.4 IOC4 — Input Capture and Output Compare Channel 4 Pin . . . . . . . . . . . . . . . . . . . . 414 13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 Freescale Semiconductor Title Chapter 12 Chapter 13 Timer Module (TIM16B4CV1) MC9S12E256 Data Sheet, Rev ...
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... CTRL — Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 14.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 14.5.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 14.5.2 Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 14.6.1 LVI — Low-Voltage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 16 Title Chapter 14 — Regulator Output2 (PLL 440 MC9S12E256 Data Sheet, Rev. 1.08 Page Freescale Semiconductor ...
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... Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 16.4.1 DBG Operating in BKP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 16.4.2 DBG Operating in DBG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 16.4.3 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 Freescale Semiconductor Title Chapter 15 Chapter 16 Debug Module (DBGV1) MC9S12E256 Data Sheet, Rev. 1.08 ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 18.4.1 Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 18.4.2 Stretched Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 18.4.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 18.4.4 Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 18.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 18 Title Chapter 17 Interrupt (INTV1) Chapter 18 MC9S12E256 Data Sheet, Rev. 1.08 Page Freescale Semiconductor ...
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... A.3.3 Phase Locked Loop 574 A.4 Flash NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 A.4.1 NVM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 A.4.2 NVM Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 A.5 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 A.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 A.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 Freescale Semiconductor Title Chapter 19 Appendix A Electrical Characteristics MC9S12E256 Data Sheet, Rev. 1.08 Contents ...
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... A.6.4 ATD Accuracy — 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 A.6.5 ATD Accuracy — 3.3V Range 588 A.7 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 A.7.1 DAC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 Ordering Information and Mechanical Drawings 20 Title Appendix B MC9S12E256 Data Sheet, Rev. 1.08 Page Freescale Semiconductor ...
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... Debugger (DBG12) including breakpoints and change-of-flow trace buffer — Multiplexed External Bus Interface (MEBI) • Wake-Up interrupt inputs — port bits available for wake up interrupt function with digital filtering • Memory — 256K Byte Flash EEPROM — 16K Byte RAM Freescale Semiconductor MC9S12E256 Data Sheet, Rev. 1.08 21 ...
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... Real Time interrupt — Clock Monitor — Pierce or low current Colpitts oscillator — Phase-locked loop clock frequency multiplier — Self Clock mode in absence of external clock — Low power 0.5 to 16Mhz crystal oscillator reference clock 22 MC9S12E256 Data Sheet, Rev. 1.08 Freescale Semiconductor ...
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... Special Test Mode (Freescale use only) — Special Peripheral Mode (Freescale use only) • Low power modes — Stop Mode — Pseudo Stop Mode — Wait Mode Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) TM mode MC9S12E256 Data Sheet, Rev. 1.08 23 ...
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... KWAD8 PAD8 AN8 KWAD9 PAD9 AN9 KWAD10 PAD10 AN10 KWAD11 PAD11 AN11 AN12 KWAD12 PAD12 AN13 KWAD13 PAD13 KWAD14 PAD14 AN14 KWAD15 AN15 PAD15 DAC0 DAO0 PM0 PM1 DAC1 DAO1 PM3 RXD2 PM4 TXD2 PM5 SDA PM6 SCL PM7 Freescale Semiconductor ...
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... Pulse Width Modulator with Fault 15-bit 6 channels (PMF) 0x0240–0x027F Port Integration Module (PIM) 0x0280–0x03FF Reserved Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Table 1-1. Device Register Map Overview Module MC9S12E256 Data Sheet, Rev. 1.08 Figure 1-2 illustrates the device ...
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... SPECIAL SINGLE CHIP MC9S12E256 Data Sheet, Rev. 1.08 1K Register Space Mappable to any 2K Boundary 16K Bytes RAM Mappable to any 16K Boundary 16K Page Window sixteen * 16K Flash EEPROM Pages 16K Fixed Flash EEPROM 2K, 4K 16K Protected Boot Sector BDM (If Active) Freescale Semiconductor ...
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... W R 0x0008 PORTE Bit 0x0009 DDRE Bit 0x000A PEAR NOACCE W R 0x000B MODE MODC W R 0x000C PUCR PUPKE W R 0x000D RDRIV RDPK 0x000E EBICTL 0x000F Reserved W Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit PIPOE NECLK LSTRE 0 MODB MODA ...
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... Bit 3 Bit 2 Bit 1 Bit RAMHAL EE11 EEON EXSTR0 ROMHM ROMON Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 ADR2 ADR1 ADR0 INT6 INT4 INT2 INT0 Bit 3 Bit 2 Bit 1 Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit 0 0 LVDS LVIE LVIF Freescale Semiconductor 0 0 ...
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... R Bit 15 0x0022 — W DBGTBL R Bit 7 0x0023 — W DBGCNT R TBF 0x0024 — W DBGCCX R 0x0025 — W Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit 4 ID14 ID13 ID12 ID6 ID5 ID4 Bit 6 Bit 5 Bit 4 0 eep_sw1 eep_sw0 rom_sw0 0 0 Bit 6 Bit 5 Bit 4 ...
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... MC9S12E256 Data Sheet, Rev. 1.08 Bit 3 Bit 2 Bit BKCEN TAGC RWCEN RWAEN RWA RWBEN EXTCMP EXTCMP Bit 3 Bit 2 Bit 1 PIX3 PIX2 PIX1 Bit 3 Bit 2 Bit 1 XAB17 XAB16 XAB15 XAB14 Freescale Semiconductor Bit 0 Bit 8 Bit 0 RWC RWB Bit 8 Bit 0 Bit 8 Bit 0 Bit 0 PIX0 0 Bit 0 Bit 0 ...
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... CFORC W FOC7 R 0x0042 OC7M OC7M7 W R 0x0043 OC7D OC7D7 W R Bit 15 0x0044 TCNT (hi Bit 7 0x0045 TCNT (lo) W Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit 4 0 SYN5 SYN4 REFDV3 TOUT6 TOUT5 TOUT4 TOUT3 0 PROF LOCKIF 0 0 LOCKIE PSTP SYSWAI ...
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... TSFRZ TFFCA TOV6 TOV5 TOV4 OL7 OM6 OL6 EDG7A EDG6B EDG6A EDG5B C6I C5I C4I TCRE C6F C5F C4F MC9S12E256 Data Sheet, Rev. 1.08 Bit 3 Bit 2 Bit 1 Bit OM5 OL5 OM4 OL4 EDG5A EDG4B EDG4A PR2 PR1 PR0 Bit 8 Freescale Semiconductor ...
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... R 0 0x0060 PACTL 0x0061 PAFLG W R 0x0062 PACNT (hi) Bit 0x0063 PACNT (lo) Bit 0x0064 Reserved 0x0065 Reserved 0x0066 Reserved 0x0067 Reserved 0x0068 Reserved 0x0069 Reserved 0x006A Reserved 0x006B Reserved W Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit PAEN PAMOD PEDGE ...
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... Bit 2 Bit Bit 3 Bit 2 Bit Bit 3 Bit 2 Bit WRAP3 WRAP2 WRAP1 WRAP0 ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 ETRIGP ETRIG ASCIE S1C FIFO FRZ1 PRS3 PRS2 PRS1 CC2 CC1 CCF11 CCF10 CCF9 Freescale Semiconductor Bit Bit 0 0 Bit ASCIF FRZ0 PRS0 CA CC0 CCF8 ...
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... R Bit15 0x009A ATDDR5H W R Bit7 0x009B ATDDR5L W R Bit15 0x009C ATDDR6H W R Bit7 0x009D ATDDR6L W Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit 4 CCF6 CCF5 CCF4 CCF3 IEN14 IEN13 IEN12 IEN11 IEN6 IEN5 IEN4 PTAD14 PTAD13 PTAD12 PTAD11 PTAD6 ...
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... ETRIGSEL and ETRIGCH0–3 bits are available in version V04 of ATD10B16C 36 Bit 6 Bit 5 Bit Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 0 0 MC9S12E256 Data Sheet, Rev. 1.08 Bit 3 Bit 2 Bit 1 Bit Bit8 Bit8 Bit8 Bit8 Bit8 Bit8 Bit8 Bit8 Bit8 Freescale Semiconductor ...
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... IREN W R 0x00D1 SCIBDL SBR7 W R 0x00D2 SCICR1 LOOPS W R 0x00D3 SCICR2 TIE W R TDRE 0x00D4 SCISR1 W Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit Bit 6 Bit 5 Bit 4 TNP1 TNP0 SBR12 SBR11 SBR6 SBR5 SBR4 SCISWAI RSRC M TCIE RIE ...
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... MC9S12E256 Data Sheet, Rev. 1.08 Bit 3 Bit 2 Bit 1 Bit 0 RAF 1 BRK13 TXDIR Bit 3 Bit 2 Bit 1 Bit 0 CPHA SSOE LSBFE 0 SPISWAI SPC0 0 SPR2 SPR1 SPR0 Bit0 Bit 3 Bit 2 Bit 1 Bit 0 ADR2 ADR1 IBC3 IBC2 IBC1 IBC0 0 0 IBSWAI RSTA 0 SRW RXAK IBIF Freescale Semiconductor ...
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... SCICR2 TIE W R TDRE 0x00EC SCISR1 0x00ED SCISR2 0x00EE SCIDRH 0x00EF SCIDRL TXPOL and RXPOL are available in version V04 of SCI Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit Bit 6 Bit 5 Bit 4 TNP1 TNP0 SBR12 SBR11 SBR6 SBR5 SBR4 ...
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... BIT0 BIT3 BIT2 BIT1 BIT0 Bit 3 Bit 2 Bit 1 Bit 0 DJM DSGN DACWAI DACOE BIT3 BIT2 BIT1 BIT0 BIT3 BIT2 BIT1 BIT0 Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit 0 FDIV2 FDIV1 FDIV0 NV3 NV2 SEC1 SEC0 FPLDIS FPLS1 FPLS0 Freescale Semiconductor ...
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... W 0x0140 – 0x016F TIM1 (Timer 16 Bit 4 Channels) (Sheet Address Name Bit 7 R 0x0140 TIOS IOS7 0x0141 CFORC W FOC7 R 0x0142 OC7M OC7M7 W R 0x0143 OC7D OC7D7 W Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit 4 CCIF PVIOL ACCERR 0 CMDB6 CMDB5 ...
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... TFFCA TOV6 TOV5 TOV4 OL7 OM6 OL6 EDG7A EDG6B EDG6A EDG5B C6I C5I C4I TCRE C6F C5F C4F MC9S12E256 Data Sheet, Rev. 1.08 Bit 3 Bit 2 Bit 1 Bit Bit Bit OM5 OL5 OM4 OL4 EDG5A EDG4B EDG4A PR2 PR1 PR0 Freescale Semiconductor ...
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... TC7 (hi) Bit 0x015F TC7 (lo) Bit 0x0160 PACTL 0x0161 PAFLG W R 0x0162 PACNT (hi) Bit 0x0163 PACNT (lo) Bit 0x0164 Reserved 0x0165 Reserved 0x0166 Reserved 0x0167 Reserved 0x0168 Reserved 0x0169 Reserved W Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit PAEN PAMOD PEDGE ...
Page 44
... FOC4 OC7M6 OC7M5 OC7M4 OC7D6 OC7D5 OC7D4 TSWAI TSFRZ TFFCA TOV6 TOV5 TOV4 OL7 OM6 OL6 MC9S12E256 Data Sheet, Rev. 1.08 Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit Bit Bit OM5 OL5 OM4 OL4 Freescale Semiconductor ...
Page 45
... R 0 0x0197 Reserved W R 0x0198 TC4 (hi) Bit 0x0199 TC4 (lo) Bit 0x015A TC5 (hi) Bit 0x019B TC5 (lo) Bit 0x019C TC6 (hi) Bit 15 W Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit EDG7A EDG6B EDG6A EDG5B C6I C5I C4I TCRE C6F C5F C4F ...
Page 46
... R 0 0x01AB Reserved 0x01AC Reserved 0x01AD Reserved 0x01AE Reserved 0x01AF Reserved W 46 Bit 6 Bit 5 Bit PAEN PAMOD PEDGE MC9S12E256 Data Sheet, Rev. 1.08 Bit 3 Bit 2 Bit 1 Bit Bit Bit Bit 0 CLK1 CLK0 PAOVI PAI 0 0 PAOVF PAIF Bit Bit Freescale Semiconductor ...
Page 47
... PWMSCNTB W R Bit 7 0x01EC PWMCNT0 Bit 7 0x01ED PWMCNT1 Bit 7 0x01EE PWMCNT2 Bit 7 0x01EF PWMCNT3 W 0 Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit Bit 6 Bit 5 Bit 4 0 PWME5 PWME4 PWME3 0 PPOL5 PPOL4 PPOL3 0 PCLK5 PCLK4 PCLK3 PCKB2 PCKB1 PCKB0 ...
Page 48
... PWMSDN PWMIF 0x01FF Reserved W 48 Bit 6 Bit 5 Bit PWMIE PWMLVL PWMRSTRT MC9S12E256 Data Sheet, Rev. 1.08 Bit 3 Bit 2 Bit 1 Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 0 0 PWM5IN PWM5INL PWM5ENA Freescale Semiconductor ...
Page 49
... R 0 0x020E PMFDTMS 0x020F PMFCCTL W R 0x0210 PMFVAL0 Bit 0x0211 PMFVAL0 Bit 0x0212 PMFVAL1 Bit 15 W Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit 4 MTG EDGEC EDGEB 0 BOTNEGC TOPNEGC 0 MSK5 MSK4 0 PMFFRZ VLMODE FIE3 FMODE2 FIE2 0 FPINE3 FPINE2 0 FFLAG3 ...
Page 50
... PMFMODA W R 0x0225 PMFMODA Bit Bit 6 Bit 5 Bit LDFQA HALFA Bit Bit MC9S12E256 Data Sheet, Rev. 1.08 Bit 3 Bit 2 Bit 1 Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit LDOKA PWMRIEA PRSCA PWMRFA Bit Bit Bit Bit 0 Freescale Semiconductor ...
Page 51
... W R 0x0231 PMFFQCC 0x0232 PMFCNTC W R 0x0233 PMFCNTC Bit 0x0234 PMFMODC W R 0x0235 PMFMODC Bit 0x0236 PMFDTMC W R 0x0237 PMFDTMC Bit 0x0238 Reserved W Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit Bit LDFQB HALFB Bit Bit Bit LDFQC HALFC ...
Page 52
... MC9S12E256 Data Sheet, Rev. 1.08 Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit 0 PTT3 PTT2 PTT1 PTT0 PTIT2 PTIT1 PTIT0 DDRT2 DDRT1 DDRT0 RDRT2 RDRT1 RDRT0 PERT2 PERT1 PERT0 PPST2 PPST1 PPST0 PTS3 PTS2 PTS1 PTS0 PTIS2 PTIS1 PTIS0 Freescale Semiconductor ...
Page 53
... R 0 0x0258 PTP 0x0259 PTIP 0x025A DDRP 0x025B RDRP 0x025C PERP W Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit 4 DDRS6 DDRS5 DDRS4 DDRS3 RDRS6 RDRS5 RDRS4 RDRS3 PERS6 PERS5 PERS4 PERS3 PPSS6 PPSS5 PPSS4 PPSS3 WOMS6 WOMS5 WOMS4 WOMS3 ...
Page 54
... PPSP2 PPSP1 PPSP0 PTQ2 PTQ1 PTQ0 PTIQ2 PTIQ1 PTIQ0 DDRQ2 DDRQ1 DDRQ0 RDRQ2 RDRQ1 RDRQ0 PERQ2 PERQ1 PERQ0 PPSQ2 PPSQ1 PPSQ0 PTU2 PTU1 PTU0 PTIU2 PTIU1 PTIU0 DDRU2 DDRU1 DDRU0 RDRU2 RDRU1 RDRU0 PERU2 PERU1 PERU0 PPSU2 PPSU1 PPSU0 Freescale Semiconductor ...
Page 55
... PIFAD7 W 0x0280 – 0x03FF Reserved Space Address Name Bit 0x0280– Reserved 0x2FF 0x0300– Unimplemented 0x03FF W Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Bit 6 Bit 5 Bit 4 PTAD14 PTAD13 PTAD12 PTAD11 PTAD6 PTAD5 PTAD4 PTAD3 PTIAD14 PTIAD13 PTIAD12 PTIAD11 PTIAD6 PTIAD5 ...
Page 56
... Mask Set Number 0L43X shows the read-only values of these registers. Refer to for further details. Table 1-3. Memory Size Registers Device Register name MEMSIZ0 MEMSIZ1 MC9S12E256 Data Sheet, Rev. 1.08 Table 1-2 shows the assigned 1 Part ID 0x5000 Chapter 19, Value 0x07 0x81 Freescale Semiconductor ...
Page 57
... IS2/PQ6 22 MODC/TAGHI/BKGD 23 IOC04/PT0 24 IOC05/PT1 25 IOC06/PT2 26 IOC07/PT3 27 IOC14/PT4 28 Signals shown in Bold are not available on the 80-pin package Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) MC9S12E256 112 LQFP Figure 1-3. Pin Assignments for 112-LQFP MC9S12E256 Data Sheet, Rev. 1.08 84 VRH 83 VDDA 82 PAD07/AN07/KWAD07 81 PAD06/AN06/KWAD06 80 ...
Page 58
... IOC04/PT0 16 IOC05/PT1 17 IOC06/PT2 18 IOC07/PT3 19 IOC14/PT4 20 58 MC9S12E256 80 QFP Figure 1-4. Pin Assignments for 80-QFP MC9S12E256 Data Sheet, Rev. 1.08 VRH 60 VDDA 59 PAD07/AN07/KWAD07 58 PAD06/AN06/KWAD06 57 PAD05/AN05/KWAD05 56 PAD04/AN04/KWAD04 55 PAD03/AN03/KWAD03 54 PAD02/AN02/KWAD02 53 PAD01/AN01/KWAD01 52 PAD00/AN00/KWAD00 51 VSS2 50 VDD2 49 PS7/SS 48 PS6/SCK 47 PS5/MOSI 46 PS4/MISO 45 PS3/TXD1 44 PS2/RXD1 43 PS1/TXD0 42 PS0/RXD0 41 Freescale Semiconductor ...
Page 59
... PM6 SDA — PM5 TXD2 — PM4 RXD2 — PM3 — — PM1 DAO1 — Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Table 1-4. Signal Properties Internal Pull Resistor Power Domain CTRL Reset State VDDPLL NA NA VDDPLL NA NA VDDPLL NA NA ...
Page 60
... Port S I/O Pin, SCI1 receive signal Port S I/O Pin, SCI0 transmit signal Port S I/O Pin, SCI0 receive signal Port T I/O Pins, timer (TIM1) Port T I/O Pins, timer (TIM0) Port U I/O Pins Port U I/O Pins, PWM outputs Port U I/O Pins, timer (TIM2), PWM outputs Freescale Semiconductor ...
Page 61
... PB[7:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PB[7:0] pins are not available in the 80 pin package version. Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Chapter 4, “Clocks and Reset Generator (CRGV4)” ...
Page 62
... IPIPE1. This pin is an input with a pull-down device which is only active when RESET is low. PE6 is not available in the 80 pin package version CDC C1 ceramic resonator C2 VSSPLL C1 RB Crystal or ceramic resonator MC9S12E256 Data Sheet, Rev. 1.08 Crystal or VSSPLL Freescale Semiconductor ...
Page 63
... MCU. During reset, the I bit in the condition code register (CCR) is set and any IRQ interrupt is masked until software enables it by clearing the I bit. The IRQ is software Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) MC9S12E256 Data Sheet, Rev. 1.08 ...
Page 64
... Interface (MEBIV3)” for further details. PK[5:0] are not available in the 80 pin package version. 64 Chapter 18, “Multiplexed External Bus Interface (MEBIV3)” for further details. PK6 is not available in the 80 pin MC9S12E256 Data Sheet, Rev. 1.08 for further Chapter 18, Chapter 18, “Multiplexed External Bus Freescale Semiconductor ...
Page 65
... PM3 is a general purpose input or output pin. While in reset and immediately out of reset the PM3 pin is configured as a high impedance input pin. Consult for information about pin configurations. Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Chapter 3, “Port Integration Module (PIM9E256V1)” ...
Page 66
... Chapter 3, “Port Integration Module (PIM9E256V1)” for information about pin configurations. MC9S12E256 Data Sheet, Rev. 1.08 Chapter 3, “Port Integration for information Chapter 3, “Port Integration for information and Chapter 11, “Pulse Width Modulator and Chapter 11, for information about pin configurations. and the Chapter 11, “Pulse and Freescale Semiconductor Chapter 9, ...
Page 67
... PS1 pin is configured as a high impedance input pin. Consult Module (PIM9E256V1)” and Chapter 8, “Serial Communication Interface (SCIV4)” about pin configurations. Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Chapter 3, “Port Integration Module (PIM9E256V1)” for information about pin configurations. and Chapter 9, “ ...
Page 68
... PW1[3:0] outputs. The MODRR register in the Port Integration Module determines if the TIM2 or PWM 68 and Chapter 13, “Timer Module (TIM16B4CV1)” and Chapter 13, “Timer Module (TIM16B4CV1)” Chapter 3, “Port Integration Module and Chapter 12, “Pulse-Width Modulator MC9S12E256 Data Sheet, Rev. 1.08 Chapter 3, “Port Integration for information Freescale Semiconductor ...
Page 69
... Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by the internal voltage regulator. Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Chapter 12, “Pulse-Width Modulator (PWM8B6CV1)” ...
Page 70
... All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on MCU pin load. 70 Description DDR SSR NOTE MC9S12E256 Data Sheet, Rev. 1.08 Freescale Semiconductor ...
Page 71
... CRG to all modules. Consult Reset Generator (CRGV4)” for details on clock generation. EXTAL OSC XTAL PE7 = XCLKS 1 0 Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Core Clock Bus Clock CRG Oscillator Clock Figure 1-7. Clock Connections Table 1-6. Clock Selection Based on PE7 Description ...
Page 72
... Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used Normal Expanded Wide, BDM allowed 1 1 Chapter 18, “Multiplexed External Bus Interface Table 1-8. Clock Selection Based on PE7 Description Colpitts Oscillator selected Pierce Oscillator/external clock selected MC9S12E256 Data Sheet, Rev. 1.08 Mode Description Freescale Semiconductor ...
Page 73
... FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) for more details on the security MC9S12E256 Data Sheet, Rev ...
Page 74
... Chapter 4, “Clocks and Reset Generator (CRGV4)” Voltage Regulator (VREG3V3V2)” 1.9.1 Vectors Table 1-9 lists interrupt sources and vectors in default order of priority. 74 Chapter 4, “Clocks and Reset Generator for detailed information on reset generation. MC9S12E256 Data Sheet, Rev. 1.08 (CRGV4)”. and Chapter 14, “Dual Output Freescale Semiconductor ...
Page 75
... Standard Timer 1 channel 5 0xFFB2, 0xFFB3 Standard Timer 1 channel 6 0xFFB0, 0xFFB1 Standard Timer 1 channel 7 0xFFAE, 0xFFAF Standard Timer 1 overflow Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Table 1-9. Interrupt Vector Locations CCR Mask None Section 4.3.2.4, “CRG to determine reset source) ...
Page 76
... PACTL (PAI) 0x9A PMFENCA (PWMRIEA) 0x98 PMFENCB (PWMRIEB) 0x96 PMFENCC (PWMRIEC) 0x94 PMFFCTL (FIE0) 0x92 PMFFCTL (FIE1) 0x90 PMFFCTL (FIE2) 0x8E PMFFCTL (FIE3) 0x8C CTRL0 (LVIE) 0x8A PWMSDN(PWMIE) 0x88 Vector 0xFFFE, 0xFFFF 0xFFFE, 0xFFFF 0xFFFE, 0xFFFF 0xFFFC, 0xFFFD 0xFFFA, 0xFFFB Freescale Semiconductor ...
Page 77
... C10 C11 R1 Q1 Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) for mode dependent pin configuration of port A, B and E out of reset. for reset configurations of all peripheral Purpose Type VDD1 filter cap Ceramic X7R Ceramic X7R VDDA filter cap Ceramic X7R VDDR filter cap ...
Page 78
... Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) VDDX C6 VSSX Figure 1-8. Recommended PCB Layout (112-LQFP) 78 NOTE: Oscillator in Colpitts mode. VSSA VSS1 VSSR VDDR Q1 VSSPLL VDDPLL R1 MC9S12E256 Data Sheet, Rev. 1.08 C3 VDDA VSS2 C2 VDD2 Freescale Semiconductor ...
Page 79
... VDDX C6 VSSX Figure 1-9. Recommended PCB Layout (80-QFP) Freescale Semiconductor Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) NOTE: Oscillator in Colpitts mode. VSS1 VSSR VDDR VSSPLL R1 VDDPLL MC9S12E256 Data Sheet, Rev. 1.08 VSSA C3 VDDA VSS2 C2 VDD2 Q1 79 ...
Page 80
... Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 80 MC9S12E256 Data Sheet, Rev. 1.08 Freescale Semiconductor ...
Page 81
... BKSEL bit in the FCNFG register. Command Write Sequence — A three-step MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. Common Register — A memory-mapped register which operates on all Flash blocks. Freescale Semiconductor CAUTION MC9S12E256 Data Sheet, Rev. 1.08 81 ...
Page 82
... Code integrity check using built-in data compression 2.1.3 Modes of Operation Program, erase, erase verify, and data compress operations (please refer to Operations” for details). 2.1.4 Block Diagram A block diagram of the Flash module is shown in 82 Figure 2-1. MC9S12E256 Data Sheet, Rev. 1.08 Section 2.4.1, “Flash Command Freescale Semiconductor ...
Page 83
... FTS256K2 Command Interrupt Request Oscillator Clock Clock Divider Freescale Semiconductor Command Interface Common Registers Banked Registers Command Pipelines Flash Block 0-1 comm1 comm2 addr1 addr2 data1 data2 Protection Security FCLK Figure 2-1. FTS256K2 Block Diagram MC9S12E256 Data Sheet, Rev. 1.08 Chapter 2 256 Kbyte Flash Module (FTS256K2V1) ...
Page 84
... Status Register (FSTAT)” 1 Refer to Section 2.3.2.9, “Flash Control Register (FCTL)” 1 Refer to Section 2.3.2.2, “Flash Security Register (FSEC)” MC9S12E256 Data Sheet, Rev. 1.08 (FPROT)”, can be set to Description Access” Reserved Flash Nonvolatile Byte Flash Security Byte Freescale Semiconductor ...
Page 85
... FLASH_START = 0x4000 0x4400 0x4800 0x5000 0x6000 0x8000 Flash Blocks 0xC000 0xE000 0xF000 0xF800 FLASH_END = 0xFFFF Note: 0x30–0x3F correspond to the PPAGE register content Freescale Semiconductor (16 bytes) Flash Registers Flash Protected Low Sectors Kbytes 0x3E 16K PAGED MEMORY 0x38 0x39 0x3A 0x3B Block 0 ...
Page 86
... Block Relative 1 Block Address 0 0x018000–0x01BFFF 1 0x000000–0x003FFF 0x004000–0x007FFF 0x008000–0x00BFFF 0x00C000–0x00FFFF 0x010000–0x013FFF 0x014000–0x017FFF 0x018000–0x01BFFF 0x01C000–0x01FFFF 0 0x000000–0x003FFF 0x004000–0x007FFF 0x008000–0x00BFFF 0x00C000–0x00FFFF 0x010000–0x013FFF 0x014000–0x017FFF 0x018000–0x01BFFF 0x01C000–0x01FFFF 0 0x01C000–0x01FFFF Freescale Semiconductor ...
Page 87
... Flash Low Data Register (FDATALO) 0x000C RESERVED1 0x000D RESERVED2 0x000E RESERVED3 0x000F RESERVED4 1 Intended for factory test purposes only. Freescale Semiconductor Chapter 2 256 Kbyte Flash Module (FTS256K2V1) Section 2.3.2, “Register Table 2-3. Flash Register Map Register Name MC9S12E256 Data Sheet, Rev. 1.08 ...
Page 88
... FPHS CCIF PVIOL ACCERR NV6 NV5 NV4 FADDRHI FADDRLO FDATAHI FDATALO Unimplemented or Reserved Figure 2-3. FTS256K2 Register Summary MC9S12E256 Data Sheet, Rev. 1. FDIV3 FDIV2 FDIV1 FDIV0 RNV3 RNV2 SEC BKSEL FPLDIS FPLS 0 BLANK 0 CMDB NV3 NV2 NV1 Freescale Semiconductor Bit NV0 0 ...
Page 89
... The oscillator clock is divided by 8 before feeding into the clock divider. 5-0 Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a FDIV[5:0] frequency of 150 kHz–200 kHz. The maximum divide ratio is 512. Please refer to FCLKDIV Register” for more information. Freescale Semiconductor ...
Page 90
... Table 2-6. Flash KEYEN States Status of Backdoor Key Access 00 DISABLED 1 01 DISABLED 10 ENABLED 11 DISABLED Table 2-7. Flash Security States Status of Security 00 SECURED 1 01 SECURED 10 UNSECURED 11 SECURED Section 2.6, “Flash Module MC9S12E256 Data Sheet, Rev. 1. RNV2 SEC Table 2-7. If the Flash Security”. Freescale Semiconductor ...
Page 91
... Field 4 Write to All Register Banks — If the WRALL bit is set, all banked registers sharing the same register address WRALL will be written simultaneously during a register write. 0 Write only to the bank selected via BKSEL. 1 Write to all register banks. Freescale Semiconductor WRALL 0 ...
Page 92
... Select register bank associated with Flash block 0. 1 Select register bank associated with Flash block KEYACC Section 2.3.2.2, “Flash Security Register Table 2-9. FCNFG Field Descriptions Description Section 2.3.2.7, “Flash Status Register (FSTAT)”) Section 2.3.2.7, “Flash Status Register MC9S12E256 Data Sheet, Rev. 1. BKSEL (FSTAT)”) Freescale Semiconductor ...
Page 93
... Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a FPHDIS protected/unprotected area in the higher address space of the Flash block. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 4:3 Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected FPHS[1:0] area as shown in Table Freescale Semiconductor FPHDIS FPHS Restrictions”). ...
Page 94
... Address Range 0x0036/0x003E: 0x8000–0x83FF 0x0036/0x003E: 0x8000–0x87FF 0x0036/0x003E: 0x8000–0x8FFF 0x0036/0x003E: 0x8000–0x9FFF Figure MC9S12E256 Data Sheet, Rev. 1.08 1 Function Paged Protected Size 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes Paged Protected Size 1 Kbyte 2 Kbytes 4 Kbytes 8 Kbytes 2-9. Although the protection scheme is Freescale Semiconductor ...
Page 95
... Scenario 0x0030–0x0035 PPAGE 0x0038–0x003D 0x0036–0x0037 PPAGE 0x003E–0x003F Unprotected region Protected region not defined by FPLS, FPHS Freescale Semiconductor FPHDIS = 1 FPHDIS = 0 FPLDIS = 0 FPLDIS = Figure 2-9. Flash Protection Scenarios MC9S12E256 Data Sheet, Rev. 1.08 Chapter 2 256 Kbyte Flash Module (FTS256K2V1) ...
Page 96
... Figure 2-10. Flash Status Register (FSTAT — Normal Mode CCIF CBEIF W Reset Unimplemented or Reserved Figure 2-11. Flash Status Register (FSTAT — Special Mode Protection Scenario PVIOL ACCERR PVIOL ACCERR MC9S12E256 Data Sheet, Rev. 1.08 Table 2-15 specifies all BLANK BLANK 0 FAIL Freescale Semiconductor ...
Page 97
... Flash block verified as not erased). The FAIL flag is cleared by writing FAIL. Writing the FAIL flag has no effect on FAIL. 0 Flash operation completed without error. 1 Flash operation failed. Freescale Semiconductor Table 2-16. FSTAT Field Descriptions Description MC9S12E256 Data Sheet, Rev. 1.08 Chapter 2 256 Kbyte Flash Module (FTS256K2V1) Figure 2-29) ...
Page 98
... Table 2-18. Valid Flash Command List CMDB[6:0] NVM Command 0x05 Erase Verify 0x06 Data Compress 0x20 Word Program 0x40 Sector Erase 0x41 Mass Erase 0x47 Sector Erase Abort MC9S12E256 Data Sheet, Rev. 1. 2-18. Writing any command other than those Freescale Semiconductor 0 0 ...
Page 99
... Unimplemented or Reserved Figure 2-15. Flash Address Low Register (FADDRLO) All FADDRHI and FADDRLO bits are readable but are not writable. After an array write as part of a command write sequence, the FADDR registers will contain the mapped MCU address written. Freescale Semiconductor NV5 ...
Page 100
... All bits read 0 and are not writable. 2.3.2.13 RESERVED2 This register is reserved for factory testing and is not accessible Reset Unimplemented or Reserved All bits read 0 and are not writable. 100 FDATAHI FDATALO Figure 2-18. RESERVED1 Figure 2-19. RESERVED2 MC9S12E256 Data Sheet, Rev. 1. Freescale Semiconductor ...
Page 101
... The next paragraphs describe: 1. How to write the FCLKDIV register. 2. Command write sequences used to program, erase, and verify the Flash memory. 3. Valid Flash commands. 4. Effects resulting from illegal Flash command write sequences or aborting Flash operations. Freescale Semiconductor Chapter 2 256 Kbyte Flash Module (FTS256K2V1 ...
Page 102
... If the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. Flash commands will not be executed if the FCLKDIV register has not been written to. 102 200 190 – 200 100 = 5% CAUTION MC9S12E256 Data Sheet, Rev. 1.08 Figure 2-22. Freescale Semiconductor ...
Page 103
... FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[ s])-1 TRY TO DECREASE Tbus YES Figure 2-22. Determination Procedure for PRDIV8 and FDIV Bits Freescale Semiconductor START NO Tbus < ALL COMMANDS IMPOSSIBLE YES PRDIV8=0 (reset) OSCILLATOR NO CLOCK > 12.8 MHZ? YES PRDIV8=1 PRDCLK=oscillator_clock PRDCLK=oscillator_clock/8 NO PRDCLK[MHz]*(5+Tbus[ s]) an integer? FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[ s])) ...
Page 104
... Section 2.4.1.3.4, “Sector Erase Section 2.4.1.3.5, “Mass Erase Section 2.4.1.3.6, “Sector Erase Abort MC9S12E256 Data Sheet, Rev. 1.08 Command”), the contents Command”), the Command”), the contents of the Command”), the contents Command”), the contents of Command”), Freescale Semiconductor ...
Page 105
... The Flash sector must not be considered erased if the ACCERR flag is set upon command completion. A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Freescale Semiconductor Chapter 2 256 Kbyte Flash Module (FTS256K2V1) Function on Flash Memory CAUTION MC9S12E256 Data Sheet, Rev ...
Page 106
... Read: Register FSTAT Bit yes Write: Register FSTAT ACCERR Clear bit ACCERR 0x10 Set? no Bit no CCIF Read: Register FSTAT Set? yes Bit no Flash Block Not Erased; BLANK Mass Erase Flash Block Set? yes EXIT MC9S12E256 Data Sheet, Rev. 1.08 Freescale Semiconductor ...
Page 107
... Flash sector must be erased using the sector erase command and then reprogrammed using the program command. The data compress command can be used to verify that a sector or sequential set of sectors are erased. Freescale Semiconductor Chapter 2 256 Kbyte Flash Module (FTS256K2V1) NOTE MC9S12E256 Data Sheet, Rev ...
Page 108
... Bit yes Write: Register FSTAT ACCERR Clear bit ACCERR 0x10 Set? no Bit no CCIF Set? yes Read: Register FDATA Data Compress Signature no Signature Valid? Flash Region Compressed yes EXIT MC9S12E256 Data Sheet, Rev. 1.08 Read: Register FSTAT Erase and Reprogram Freescale Semiconductor ...
Page 109
... Error Check Address, Data, Command Buffer Empty Check Bit Polling for Command Completion Check Figure 2-25. Example Program Command Flow Freescale Semiconductor no Write: Register FCLKDIV NOTE: command write sequence aborted by writing 0x00 to FSTAT register. NOTE: command write sequence aborted by writing 0x00 to FSTAT register ...
Page 110
... Write: Register FSTAT PVIOL Clear bit PVIOL 0x20 Set? no Bit yes Write: Register FSTAT ACCERR Clear bit ACCERR 0x10 Set? no Bit yes CBEIF Set? no Bit no CCIF Read: Register FSTAT Set? yes EXIT MC9S12E256 Data Sheet, Rev. 1.08 yes Next Write? no Freescale Semiconductor ...
Page 111
... Error Check Address, Data, Command Buffer Empty Check Bit Polling for Command Completion Check Figure 2-27. Example Mass Erase Command Flow Freescale Semiconductor no Write: Register FCLKDIV NOTE: command write sequence aborted by writing 0x00 to FSTAT register. NOTE: command write sequence aborted by writing 0x00 to FSTAT register ...
Page 112
... ACCERR flag, if set. The sector erase abort command must be used sparingly because a sector erase operation that is aborted counts as a complete program/erase cycle. 112 NOTE NOTE MC9S12E256 Data Sheet, Rev. 1.08 Section 2.4.1.1, “Writing the Freescale Semiconductor ...
Page 113
... Bit Polling for Command Completion Check NOTE: command write sequence aborted by writing 0x00 to FSTAT register. NOTE: command write sequence aborted by writing 0x00 to FSTAT register. Figure 2-28. Example Sector Erase Abort Command Flow Freescale Semiconductor Bit Erase no CCIF Abort Set? Needed? yes yes ...
Page 114
... Writing the sector erase command if the address written in the command write sequence was in a protected area of the Flash memory. 3. Writing the mass erase command while any Flash protection is enabled. 114 Section 2.4.1.3.6, “Sector Erase Abort Section 2.3.2.7, “Flash Status Register MC9S12E256 Data Sheet, Rev. 1.08 Section 2.5.2, “Stop Mode”). (FSTAT)”). Freescale Semiconductor ...
Page 115
... MCU is unsecured and the higher address sector is unprotected. If the Flash security byte remains in a secured state, any reset will cause the MCU to initialize to a secure operating mode. Freescale Semiconductor Chapter 2 256 Kbyte Flash Module (FTS256K2V1) Sequence”). ...
Page 116
... After the next reset of the MCU, the security state of the Flash module 116 Section 2.3.2.2, “Flash Security Register Section 2.3.2.2, “Flash Security Register MC9S12E256 Data Sheet, Rev. 1.08 (FSEC)”) and the (FSEC)”), Freescale Semiconductor ...
Page 117
... Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector / block being erased is not guaranteed. Freescale Semiconductor Chapter 2 256 Kbyte Flash Module (FTS256K2V1) Table 2-1: Section 2.3.2.5, “ ...
Page 118
... CCIF (FSTAT register) NOTE Figure 2-29. CBEIE CCIE Figure 2-29. Flash Interrupt Implementation Section 2.3.2.4, “Flash Configuration Register (FSTAT)”. MC9S12E256 Data Sheet, Rev. 1.08 Local Enable Global (CCR) Mask I Bit CCIE (FCNFG register) I Bit Flash Command Interrupt Request Freescale Semiconductor ...
Page 119
... Input with selectable pull-up or pull-down device Optional features: • Open drain for wired-OR connections • Interrupt input with glitch filtering Freescale Semiconductor NOTE MC9S12E256 Data Sheet, Rev. 1.08 for details on 119 ...
Page 120
... PW04 PP4 PW05 PP5 RXD PS0 TXD PS1 RXD PS2 TXD PS3 PS4 PS5 SCK PS6 SS PS7 BKGD XIRQ PE0 IRQ PE1 R/W PE2 PE3 ECLK PE4 PE5 PE6 PE7 PK0 PK1 PK2 PK3 PK4 PK5 XCS PK6 PK7 Freescale Semiconductor ...
Page 121
... ADDR11/DATA11 Refer to GPIO PA2 ADDR10/DATA10 Refer to GPIO PA1 ADDR9/DATA9 GPIO PA0 ADDR8/DATA8 GPIO Freescale Semiconductor Description Refer to Chapter 18, “Multiplexed External Bus Interface (MEBIV3)” Refer to Chapter 15, “Background Debug Module (BDMV4)” Refer to Chapter 18, “Multiplexed External Bus Interface (MEBIV3)” Chapter 18, “Multiplexed External Bus Interface (MEBIV3)” ...
Page 122
... General-purpose I/O Refer to Chapter 18, “Multiplexed External Bus Interface (MEBIV3)” General-purpose I/O MC9S12E256 Data Sheet, Rev. 1.08 Pin Function after Reset Refer to Chapter 18, “Multiplexed External Bus Interface (MEBIV3)” Refer to Chapter 18, “Multiplexed External Bus Interface (MEBIV3)” Freescale Semiconductor ...
Page 123
... PK3 XADDR17 GPIO PK2 XADDR16 GPIO PK1 XADDR15 GPIO PK0 XADDR14 GPIO Freescale Semiconductor Description Refer to Chapter 18, “Multiplexed External Bus Interface (MEBIV3)” General-purpose I/O Refer to Chapter 18, “Multiplexed External Bus Interface (MEBIV3)” General-purpose I/O Refer to Chapter 18, “Multiplexed External Bus Interface (MEBIV3)” ...
Page 124
... General-purpose I/O Analog-to-digital converter input channel 2 Keyboard wake-up interrupt 2 General-purpose I/O Analog-to-digital converter input channel 1 Keyboard wake-up interrupt 1 General-purpose I/O Analog-to-digital converter input channel 0 Keyboard wake-up interrupt 0 General-purpose I/O MC9S12E256 Data Sheet, Rev. 1.08 Pin Function after Reset GPIO Freescale Semiconductor ...
Page 125
... GPIO PQ2 FAULT2 GPIO PQ1 FAULT11 GPIO PQ0 FAULT0 GPIO Freescale Semiconductor Description Inter-integrated circuit serial clock line General-purpose I/O Inter-integrated circuit serial data line General-purpose I/O Serial communication interface 2 transmit pin General-purpose I/O Serial communication interface 2 receive pin General-purpose I/O ...
Page 126
... Timer 1 channel 6 General-purpose I/O Timer 1 channel 5 General-purpose I/O Timer 1 channel 4 General-purpose I/O Timer 0 channel 7 General-purpose I/O Timer 0 channel 6 General-purpose I/O Timer 0 channel 5 General-purpose I/O Timer 0 channel 4 General-purpose I/O MC9S12E256 Data Sheet, Rev. 1.08 Pin Function after Reset GPIO GPIO Freescale Semiconductor ...
Page 127
... PU2 IOC2 PW12 GPIO PU1 IOC1 PW11 GPIO PU0 IOC0 PW11 GPIO Freescale Semiconductor Description General-purpose I/O General-purpose I/O Pulse-width modulator 1 channel 5 General-purpose I/O Pulse-width modulator 1 channel 4 General-purpose I/O Timer 2 channel 7 Pulse-width modulator 1 channel 3 General-purpose I/O Timer 2 channel 6 Pulse-width modulator 1 channel 2 ...
Page 128
... Table 3-2. PIM9HZ256 Memory Map Use MC9S12E256 Data Sheet, Rev. 1. standard memory map of port Access R/W R R/W R/W R/W R/W — R/W R R/W R/W R/W R/W R/W — R/W R R/W R/W R/W R/W R/W — R/W R R/W R/W R/W R/W — Freescale Semiconductor ...
Page 129
... Port AD Polarity Select Register (PPSAD) 0x003B 0x003D Port AD Interrupt Enable Register (PIEAD) 0x003D 0x003E Port AD Interrupt Flag Register (PIFAD) 0x003F Freescale Semiconductor Chapter 3 Port Integration Module (PIM9E256V1) Use MC9S12E256 Data Sheet, Rev. 1.08 Access R/W R R/W R/W R/W R/W — ...
Page 130
... KWAD5 KWAD4 KWAD3 AN5 AN4 AN3 Figure 3-2. Port AD I/O Register (PTAD) MC9S12E256 Data Sheet, Rev. 1.08 for information on the ATDDIEN0 PTAD10 PTAD9 PTAD8 KWAD10 KWAD9 KWAD8 AN10 AN9 AN8 PTAD2 PTAD1 PTAD0 KWAD2 KWAD1 KWAD0 AN2 AN1 AN0 Freescale Semiconductor ...
Page 131
... ATDDIEN0(1) bit. If the associated ATDDIEN0(1) bit is set to 1 (digital input buffer is enabled), a read on PTADx returns the value on port AD pin. If the associated ATDDIEN0(1) bit is set to 0 (digital input buffer is disabled), a read on PTADx returns a 1. Field 15:0 Data Direction Port AD DDRAD[15:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. Freescale Semiconductor PTIAD13 PTIAD12 PTIAD11 1 1 ...
Page 132
... RDRAD12 RDRAD11 RDRAD5 RDRAD4 RDRAD3 Table 3-4. RDRAD Field Descriptions Description PERAD13 PERAD12 PERAD11 PERAD5 PERAD4 PERAD3 Table 3-5. PERAD Field Descriptions Description MC9S12E256 Data Sheet, Rev. 1. RDRAD10 RDRAD9 RDRAD8 RDRAD2 RDRAD1 RDRAD0 PERAD10 PERAD9 PERAD8 PERAD2 PERAD1 PERAD0 Freescale Semiconductor ...
Page 133
... AD pin sets the corresponding PIFADx bit. Field 15:0 Polarity Select Port AD PPSAD[15: pull-up device is connected to the associated port AD pin, and detects falling edge for interrupt generation pull-down device is connected to the associated port AD pin, and detects rising edge for interrupt generation. Freescale Semiconductor PPSAD13 PPSAD12 PPSAD11 0 ...
Page 134
... This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port AD. Field 15:0 Interrupt Enable Port AD PIEAD[15:0] 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. 134 PIEAD13 PIEAD12 PIEAD11 PIEAD5 PIEAD4 PIEAD3 Table 3-7. PIEAD Field Descriptions Description MC9S12E256 Data Sheet, Rev. 1. PIEAD10 PIEAD9 PIEAD8 PIEAD2 PIEAD1 PIEAD0 Freescale Semiconductor ...
Page 135
... Field 15:0 Interrupt Flags Port AD PIFAD[15: active edge pending. Writing a “0” has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a “1” clears the associated flag. Freescale Semiconductor PIFAD13 PIFAD12 PIFAD11 ...
Page 136
... IIC bus. for information on enabling and disabling PTM5 PTM4 PTM3 TXD2 RXD2 Figure 3-10. Port M I/O Register (PTM) MC9S12E256 Data Sheet, Rev. 1.08 Chapter 10, for information on enabling and PTM1 PTM0 DAO1 DAO0 0 0 Freescale Semiconductor 0 0 ...
Page 137
... The DDRM bits do not change to reflect the pin I/O direction when not being used as GPIO. The DDRM[7:3]; DDRM[1:0] bits revert to controlling the I/O direction of the pins when the associated IIC, SCI, or DAC1/0 function are disabled. Field 7:3, 1:0 Data Direction Port M DDRM[7:3, 0 Associated pin is configured as input. 1:0] 1 Associated pin is configured as output. Freescale Semiconductor PTIM5 PTIM4 PTIM3 Unaffected by reset Figure 3-11 ...
Page 138
... Pull Device Enable Port M PERM[7:3, 0 Pull-up or pull-down device is disabled. 1:0] 1 Pull-up or pull-down device is enabled. 138 RDRM5 RDRM4 RDRM3 Table 3-10. RDRM Field Descriptions Description PERM5 PERM4 PERM3 Table 3-11. PERM Field Descriptions Description MC9S12E256 Data Sheet, Rev. 1. RDRM1 RDRM0 PERM1 PERM0 Freescale Semiconductor ...
Page 139
... The Port M Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. Field 7:3, 1:0 Pull Select Port M PPSM[7: pull-up device is connected to the associated port M pin. 1: pull-down device is connected to the associated port M pin. Freescale Semiconductor PPSM5 PPSM4 PPSM3 Table 3-12 ...
Page 140
... WOMM[7:6] bits have no effect. The WOMM[7:6] bits will not change to reflect their wired-OR mode configuration when the IIC is enabled. Field 7:4 Wired-OR Mode Port M WOMM[7:4] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. 140 WOMM5 WOMM4 Table 3-13. WOMM Field Descriptions Description MC9S12E256 Data Sheet, Rev. 1. Freescale Semiconductor ...
Page 141
... Port P Input Register (PTIP Reset Reserved or Unimplemented Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. Freescale Semiconductor PTP5 PTP4 PTP3 PW05 PW04 PW03 Figure 3-17. Port P I/O Register (PTP) ...
Page 142
... Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. 142 DDRP5 DDRP4 DDRP3 Table 3-14. DDRP Field Descriptions Description RDRP5 RDRP4 RDRP3 Table 3-15. RDRP Field Descriptions Description MC9S12E256 Data Sheet, Rev. 1. DDRP2 DDRP1 DDRP0 RDRP2 RDRP1 RDRP0 Freescale Semiconductor ...
Page 143
... The Port P Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. Field 5:0 Polarity Select Port P PPSP[5: pull-up device is connected to the associated port P pin pull-down device is connected to the associated port P pin. Freescale Semiconductor PERP5 PERP4 PERP3 0 ...
Page 144
... PTQ5 PTQ4 PTQ3 IS1 IS0 FAULT3 Figure 3-23. Port Q I/O Register (PTQ PTIQ5 PTIQ4 PTIQ3 Unaffected by reset Figure 3-24. Port Q Input Register (PTIQ) MC9S12E256 Data Sheet, Rev. 1.08 for information PTQ2 PTQ1 PTQ0 FAULT2 FAULT1 FAULT0 PTIQ2 PTIQ1 PTIQ0 Freescale Semiconductor ...
Page 145
... This register configures the drive strength of configured output pins as either full or reduced pin is configured as input, the corresponding Reduced Drive Register bit has no effect. Field 6:0 Reduced Drive Port Q RDRQ[6:0] 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. Freescale Semiconductor DDRQ5 DDRQ4 DDRQ3 0 ...
Page 146
... A pull-up device is connected to the associated port Q pin pull-down device is connected to the associated port Q pin. 146 PERQ5 PERQ4 PERQ3 Table 3-20. PERQ Field Descriptions Description PPSQ5 PPSQ4 PPSQ3 Table 3-21. PPSQ Field Descriptions Description MC9S12E256 Data Sheet, Rev. 1. PERQ2 PERQ1 PERQ0 PPSQ2 PPSQ1 PPSQ0 Freescale Semiconductor ...
Page 147
... Port S Input Register (PTIS PTIS7 PTIS6 W Reset Reserved or Unimplemented Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. Freescale Semiconductor for information on enabling and disabling the SPI PTS5 PTS4 PTS3 MOSI MISO TXD1 Figure 3-29 ...
Page 148
... If the SPI, SCI1 and SCI0 functions are disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. Field 7:0 Data Direction Port S DDRS[7:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. 148 DDRS5 DDRS4 DDRS3 Table 3-22. DDRS Field Descriptions Description MC9S12E256 Data Sheet, Rev. 1. DDRS2 DDRS1 DDRS0 Freescale Semiconductor ...
Page 149
... This register configures whether a pull- pull-down device is activated on configured input or wired-OR (open drain) output pins pin is configured as push-pull output, the corresponding Pull Device Enable Register bit has no effect. Field 7:0 Pull Device Enable Port S PERS[7:0] 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Freescale Semiconductor RDRS5 RDRS4 RDRS3 Table 3-23 ...
Page 150
... Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. 150 PPSS5 PPSS4 PPSS3 Table 3-25. PPSS Field Descriptions Description WOMS5 WOMS4 WOMS3 Table 3-26. WOMS Field Descriptions Description MC9S12E256 Data Sheet, Rev. 1. PPSS2 PPSS1 PPSS0 WOMS2 WOMS1 WOMS0 Freescale Semiconductor ...
Page 151
... Port T Input Register (PTIT PTIT7 PTIT6 W Reset Reserved or Unimplemented Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. Freescale Semiconductor for information on enabling and disabling the TIM PTT5 PTT4 PTT3 OC15 OC14 OC07 Figure 3-36 ...
Page 152
... Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. 152 DDRT5 DDRT4 DDRT3 Table 3-27. DDRT Field Descriptions Description RDRT5 RDRT4 RDRT3 Table 3-28. RDRT Field Descriptions Description MC9S12E256 Data Sheet, Rev. 1. DDRT2 DDRT1 DDRT0 RDRT2 RDRT1 RDRT0 Freescale Semiconductor ...
Page 153
... The Port T Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. Field 7:0 Pull Select Port T PPST[7: pull-up device is connected to the associated port T pin pull-down device is connected to the associated port T pin. Freescale Semiconductor PERT5 PERT4 PERT3 0 ...
Page 154
... PTIU5 PTIU4 PTIU3 Unaffected by reset Figure 3-43. Port U Input Register (PTIU) MC9S12E256 Data Sheet, Rev. 1.08 for information on enabling and disabling Chapter 3, “Port 2 1 PTU2 PTU1 PW12 PW11 OC26 OC25 PTIU2 PTIU1 u u Freescale Semiconductor 0 PTU0 PW10 OC24 0 0 PTIU0 u ...
Page 155
... When both a timer function and a PWM function are enabled on the same pin, the MODRR register determines which function has control of the pin Field 7:0 Data Direction Port U DDRU[7:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. Freescale Semiconductor DDRU5 DDRU4 DDRU3 0 ...
Page 156
... Pull Device Enable Port U PERU[7:0] 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. 156 RDRU5 RDRU4 RDRU3 Table 3-32. RDRU Field Descriptions Description PERU5 PERU4 PERU3 Table 3-33. PERU Field Descriptions Description MC9S12E256 Data Sheet, Rev. 1. RDRU2 RDRU1 RDRU0 PERU2 PERU1 PERU0 Freescale Semiconductor ...
Page 157
... Figure 3-48. Port U Module Routing Register (MODRR) Read: Anytime. Write: Anytime. This register selects the module connected to port U. Field 3:0 Pull Select Port U MODRR[3: enabled, TIM2 channel is connected to the associated port U pin enabled, PWM channel is connected to the associated port U pin. Freescale Semiconductor PPSU5 PPSU4 PPSU3 Table 3-34 ...
Page 158
... Register bit set to 0 configures the pin as an input. A Data Direction Register bit set to 0 configures the pin as an output peripheral module controls the pin the contents of the data direction register is ignored (Figure 3-49). 158 MC9S12E256 Data Sheet, Rev. 1.08 (Figure 3-49). (Figure 3-49). It can Freescale Semiconductor ...
Page 159
... If the port is used as an output the Reduced Drive Register allows the configuration of the drive strength. 3.4.5 Pull Device Enable Register The Pull Device Enable Register turns on a pull-up or pull-down device. The pull device becomes active only if the pin is used as an input wired-OR output. Freescale Semiconductor PTIx 0 1 PTx ...
Page 160
... Disabled Pull Up Disabled Pull Down Disabled Disabled Falling Edge Disabled Rising Edge Pull Up Falling Edge Pull Down Rising Edge Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Falling Edge Disabled Rising Edge Disabled Falling Edge Disabled Rising Edge Freescale Semiconductor ...
Page 161
... BKGD pin AD Input M[7:4] Input M[3,1:0] Input P Input Q Input S Input T Input U Input Freescale Semiconductor Table 3-37. Port Reset State Summary Reset States Pull Mode Red. Drive Pull Up Refer to Chapter 18, “Multiplexed External Bus Hi-z Disabled Pull Up Disabled Hi-z Disabled Hi-z Disabled Hi-z ...
Page 162
... Table 3-38. Pulse Detection Criteria Mode STOP Unit t <= 3 Bus Clock pulse 3 < t < 4 Bus Clock 3.2 < t pulse t >= 4 Bus Clock pulse MC9S12E256 Data Sheet, Rev. 1.08 (Figure 3-51 1 STOP Unit t <= 3.2 s pulse < pulse t > pulse Freescale Semiconductor and ...
Page 163
... Operation in Stop Mode All clocks are stopped in STOP mode. The port integration module has asynchronous paths on port AD to generate wake-up interrupts from stop mode. For other sources of external interrupts refer to the respective block description chapters. Freescale Semiconductor t pulse Figure 3-52. Pulse Illustration ...
Page 164
... Chapter 3 Port Integration Module (PIM9E256V1) 164 MC9S12E256 Data Sheet, Rev. 1.08 Freescale Semiconductor ...
Page 165
... System reset generation from the following possible sources: — Power-on reset — Low voltage reset Refer to the device overview section for availability of this feature. — COP reset — Loss of clock reset — External pin reset • Real-time interrupt (RTI) Freescale Semiconductor MC9S12E256 Data Sheet, Rev. 1.08 165 ...
Page 166
... Self-clock mode should be used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions. 4.1.3 Block Diagram Figure 4-1 shows a block diagram of the CRGV4. 166 MC9S12E256 Data Sheet, Rev. 1.08 Freescale Semiconductor ...
Page 167
... VCO input ripple. The value of the external filter network and the reference frequency determines the speed of the corrections and the stability of the PLL. Refer to Device Overview (MC9S12E256DGV1)” usage is not required the XFC pin must be tied to V Freescale Semiconductor Power-on Reset 1 Low Voltage Reset ...
Page 168
... CTCTL is intended for factory test purposes only. 168 CS MCU RS XFC Figure 4-2. PLL Loop Filter Connections Table 4-1. CRGV4 Memory Map Use MC9S12E256 Data Sheet, Rev. 1.08 V DDPLL CP Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Freescale Semiconductor ...
Page 169
... REFDV CTFLG CRGFLG R RTIF W CRGINT R RTIE W CLKSEL R PLLSEL W PLLCTL R CME W RTICTL COPCTL R WCOP W FORBYP CTCTL Freescale Semiconductor NOTE SYN5 SYN4 REFDV3 PORF LVRF LOCKIF 0 0 LOCKIE PSTP SYSWAI ROAWAI PLLON AUTO ACQ RTR6 RTR5 RTR4 0 0 RSBCK Unimplemented or Reserved Figure 4-3. CRG Register Summary MC9S12E256 Data Sheet, Rev ...
Page 170
... Write to this register initializes the lock detector bit and the track detector bit. 170 Bit 6 Bit 5 Bit 4 = Unimplemented or Reserved SYNR = ---------------------------------- - PLLCLK 2xOSCCLKx REFDV NOTE SYN5 SYNR SYN3 NOTE MC9S12E256 Data Sheet, Rev. 1. Bit Bit 3 Bit 2 Bit 1 Bit 0 ). SCM + SYN2 SYN1 0 0 Freescale Semiconductor 0 0 SYN0 0 ...
Page 171
... W Reset Unimplemented or Reserved Figure 4-6. CRG Reserved Register (CTFLG) Read: always reads 0x0000 in normal modes Write: unimplemented in normal modes Writing to this register when in special mode can alter the CRGV4 functionality. Freescale Semiconductor Chapter 4 Clocks and Reset Generator (CRGV4 REFDV3 NOTE ...
Page 172
... Track Status Bit — TRACK reflects the current state of PLL track condition. This bit is cleared in self-clock mode. TRACK Writes have no effect. 0 Acquisition mode status. 1 Tracking mode status. 172 LOCK LVRF LOCKIF Note Figure 4-7. CRG Flag Register (CRGFLG) Table 4-2. CRGFLG Field Descriptions Description MC9S12E256 Data Sheet, Rev. 1. TRACK SCM SCMIF Chapter 1, “MC9S12E256 Device Freescale Semiconductor ...
Page 173
... Interrupt will be requested whenever RTIF is set. 4 Lock Interrupt Enable Bit LOCKIE 0 LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. 1 Self-Clock Mode Interrupt Enable Bit SCMIE 0 SCM interrupt requests are disabled. 1 Interrupt will be requested whenever SCMIF is set. Freescale Semiconductor Description . SCM LOCKIE 0 ...
Page 174
... Core clock keeps running in wait mode. 1 Core clock stops in wait mode. 174 Figure 4- SYSWAI ROAWAI PLLWAI Table 4-4. CLKSEL Field Descriptions Description MC9S12E256 Data Sheet, Rev. 1.08 for details on the effect of each bit CWAI RTIWAI COPWAI 0 0 Chapter 5, “Oscillator (OSCV2)” Freescale Semiconductor 0 0 ...
Page 175
... Automatic mode control is disabled and the PLL is under software control, using ACQ bit. 1 Automatic mode control is enabled and ACQ bit has no effect. 4 Acquisition Bit — Write anytime. If AUTO=1 this bit has no effect. ACQ 0 Low bandwidth filter is selected. 1 High bandwidth filter is selected. Freescale Semiconductor Description AUTO ...
Page 176
... Table 4-6. RTICTL Field Descriptions Description Table 4-7 shows all possible divide values selectable by the RTICTL register. The MC9S12E256 Data Sheet, Rev. 1.08 Section 4.5.1, “Clock Monitor Reset”). Section 4.4.7.2, “Self-Clock Mode”). RTR2 RTR1 RTR0 Table Freescale Semiconductor 4-7. ...
Page 177
... OFF* 1100 ( ³13) OFF* 1101 ( 14) OFF* 1110 (³ 15) OFF* 1111 ( ³16) * Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. Freescale Semiconductor Table 4-7. RTI Frequency Divide Rates RTR[6:4] = 001 010 011 ...
Page 178
... ARMCOP register) 178 Table 4-8. COPCTL Field Descriptions Description Table 4-9. COP Watchdog Rates OSCCLK CR1 CR0 Cycles to Time Out 0 0 COP disabled MC9S12E256 Data Sheet, Rev. 1. CR2 CR1 0 0 Table 4-9 Table 4-9). The COP Freescale Semiconductor 0 CR0 0 shows ...
Page 179
... Writing to this register when in special test modes can alter the CRG’s functionality Reset Unimplemented or Reserved Read: always read 0x0080 except in special modes Write: only in special modes Freescale Semiconductor NOTE Figure 4-13. Reserved Register (FORBYP) NOTE 5 ...
Page 180
... The PLL can change between acquisition and tracking modes either automatically or manually. 180 Bit 5 Bit 4 Bit Figure 4-15. ARMCOP Register Diagram SYNR ---------------------------------- - PLLCLK = 2 OSCCLK REFDV CAUTION MC9S12E256 Data Sheet, Rev. 1. Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 181
... The lock detector compares the frequencies of the feedback clock, and the reference clock. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison. Freescale Semiconductor REFERENCE REFDV <3:0> ...
Page 182
... The following conditions apply when in sys MC9S12E256 Data Sheet, Rev. 1.08 , and is clear when trk , and is cleared Lock . ) before acq ) before selecting the PLLCLK al Freescale Semiconductor ...
Page 183
... PLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the PLL output clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum Freescale Semiconductor PLLSEL or SCM 1 ...
Page 184
... A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that osc ok immediately terminates the current check window. See 1. VCO clock cycles are generated by the PLL when running at minimum frequency f 184 1 is called check window. Figure 4-19 MC9S12E256 Data Sheet, Rev. 1. example. . SCM Freescale Semiconductor ...
Page 185
... Figure 4-20. Sequence for Clock Quality Check Remember that in parallel to additional actions caused by self-clock mode or clock monitor reset check the OSCCLK signal Clock Monitor Reset will always set the SCME bit to logical’1’ Freescale Semiconductor check window 4096 4095 osc ok Figure 4-19 ...
Page 186
... SCM CR[2:0] 0:0:0 16384 Figure 4-21. Clock Chain for COP Reset).” The COP runs with a gated OSCCLK (see MC9S12E256 Data Sheet, Rev. 1.08 ) and an active VREG CR[2:0] 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 COP TIMEOUT Section 4.5.2, Freescale Semiconductor ...
Page 187
... The CRGV4 block behaves as described within this specification in all normal modes. 4.4.7.2 Self-Clock Mode The VCO has a minimum operating frequency failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO Freescale Semiconductor . WAIT(RTIWAI), RTI enable 1024 ...
Page 188
... MC9S12E256 Data Sheet, Rev. 1.08 Section 4.4.4, “Clock Quality COPWAI ROAWAI — — — — — — — — stopped — 1 — reduced Figure 4-23). Depending on Freescale Semiconductor ...
Page 189
... Core req’s Wait Mode. no PLLWAI=1 ? yes CWAI or Clear PLLSEL, SYSWAI=1 Disable PLL ? yes Disable core clocks Figure 4-23. Wait Mode Entry/Exit Sequence Freescale Semiconductor no no SYSWAI=1 ? yes Disable Enter system clocks Wait Mode Wait Mode left due to external reset Exit Wait w. ext.RESET no Exit Wait w ...
Page 190
... If wait mode is entered from self-clock mode, the CRG will continue to check the clock quality until clock check is successful. The PLL and voltage regulator (VREG) will remain enabled. Table 4-11 summarizes the outcome of a clock loss while in wait mode. 190 MC9S12E256 Data Sheet, Rev. 1.08 Section 4.4.4, “Clock Freescale Semiconductor ...
Page 191
... Continue to perform additional Clock Quality Checks until OSCCLK or an External RESET is applied. – Exit Wait Mode in SCM using PLL clock (f – Start reset sequence, – Continue to perform additional Clock Quality Checks until OSCCLK Freescale Semiconductor CRG Actions while in Wait Mode. is o.k. again. is o.k.again. ...
Page 192
... A complete timeout window check will be started when stop mode is exited again. Wake-up from stop mode also depends on the setting of the PSTP bit. 192 CRG Actions ) as system clock, SCM MC9S12E256 Data Sheet, Rev. 1.08 Freescale Semiconductor ...
Page 193
... Exit Stop w. ext.RESET Exit Stop w. SCME=1 CMRESET ? yes Exit Stop Mode Enter SCM Figure 4-24. Stop Mode Entry/Exit Sequence Freescale Semiconductor Core req’s Stop Mode. Clear PLLSEL, Disable PLL Wait Mode left Enter due to external Stop Mode no yes INT PSTP=1 ? ...
Page 194
... MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 4-12 summarizes the outcome of a clock loss while in pseudo-stop mode. 194 MC9S12E256 Data Sheet, Rev. 1.08 Section 4.4.4, “Clock Freescale Semiconductor ...
Page 195
... External RESET is applied. – Exit Pseudo-Stop Mode in SCM using PLL clock (f – Start reset sequence, – Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. Freescale Semiconductor Chapter 4 Clocks and Reset Generator (CRGV4) CRG Actions MC9S12E256 Data Sheet, Rev. 1. system clock ...
Page 196
... The reset values of registers and signals are provided in 196 CRG Actions SCM Checker”). After completing the clock quality check Checker”). If the clock quality check is successful, the NOTE Section 4.3, “Memory Map and Register MC9S12E256 Data Sheet, Rev. 1. system clock, Freescale Semiconductor ...
Page 197
... External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic 1 within 64 SYSCLK cycles after the low drive is released. Freescale Semiconductor Table 4-13. Refer to for related vector addresses and priorities. ...
Page 198
... CRG drives RESET pin low RESET pin released ) ( 128+n cycles 64 cycles with n being possibly min 3 / max 6 SYSCLK cycles depending not on internal running synchronization delay Figure 4-25. RESET Timing MC9S12E256 Data Sheet, Rev. 1. possibly RESET driven low externally Section 4.3, Freescale Semiconductor ...
Page 199
... Internal RESET Figure 4-26. RESET Pin Tied to V RESET Internal POR Internal RESET Figure 4-27. RESET Pin Held Low Externally Freescale Semiconductor Chapter 4 Clocks and Reset Generator (CRGV4) to the MCU has reached a certain level and asserts DD Clock Quality Check (no Self-Clock Mode) ...
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... Table 4-15. CRG Interrupt Vectors CCR Local Enable Mask I bit CRGINT (RTIE) I bit CRGINT (LOCKIE) I bit CRGINT (SCMIE) Section 4.4.4, “Clock Quality MC9S12E256 Data Sheet, Rev. 1.08 4-15. Refer to Chapter 1, Checker.” If the clock monitor Freescale Semiconductor ...