MC9S12E256MFUE Freescale Semiconductor, MC9S12E256MFUE Datasheet - Page 460

• Manufacturer Part Number: MC9S12E256MFUE
• Description: IC MCU 256K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256MFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 60
• Ram Memory Size: 16KB
• Cpu Speed: 25MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 15 Background Debug Module (BDMV4)
Figure 15-9
target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of
the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Because the
target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly
drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after
starting the bit time.
460
TARGET SYSTEM
TARGET SYSTEM
SPEEDUP PULSE
TARGET SYS.
START OF BIT TIME
TARGET SYS.
START OF BIT TIME
BKGD PIN
DRIVE AND
BKGD PIN
SPEEDUP
DRIVE TO
BKGD PIN
DRIVE TO
BKGD PIN
CLOCK
CLOCK
PULSE
HOST
PERCEIVED
HOST
PERCEIVED
shows the host receiving a logic 0 from the target. Because the host is asynchronous to the
Figure 15-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 15-9. BDM Target-to-Host Serial Bit Timing (Logic 0)
HIGH-IMPEDANCE
10 CYCLES
10 CYCLES
MC9S12E256 Data Sheet, Rev. 1.08
R-C RISE
10 CYCLES
10 CYCLES
HIGH-IMPEDANCE
HOST SAMPLES
HIGH-IMPEDANCE
HOST SAMPLES
BKGD PIN
BKGD PIN
SPEEDUP PULSE
HIGH-IMPEDANCE
Freescale Semiconductor
EARLIEST
START OF
NEXT BIT
EARLIEST
START OF
NEXT BIT