MC9S12E256MFUE Freescale Semiconductor, MC9S12E256MFUE Datasheet - Page 402

• Manufacturer Part Number: MC9S12E256MFUE
• Description: IC MCU 256K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256MFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 60
• Ram Memory Size: 16KB
• Cpu Speed: 25MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 12 Pulse-Width Modulator (PWM8B6CV1)
12.4.1.3
Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock
choices are clock A or clock SA. For channels 2 and 3 the choices are clock B or clock SB. The clock
selection is done with the PCLKx control bits in the PWMCLK register.
12.4.2
The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period
register and a duty register (each are 8 bit). The waveform output period is controlled by a match between
the period register and the value in the counter. The duty is controlled by a match between the duty register
and the counter value and causes the state of the output to change during the period. The starting polarity
of the output is also selectable on a per channel basis.
402
Clock Source
PWMEx
(clock edge sync)
PWM Channel Timers
Clock Select
GATE
Changing clock control bits while channels are operating can cause
irregularities in the PWM outputs.
up/down
reset
Figure 12-35. PWM Timer Channel Block Diagram
8-Bit Counter
PWMCNTx
Q
Q
T
R
MC9S12E256 Data Sheet, Rev. 1.08
NOTE
Figure 12-35
8-Bit Compare =
8-Bit Compare =
PWMDTYx
PWMPERx
CAEx
shows a block diagram for PWM timer.
T
R
Q
Q
PPOLx
M
U
X
From Port PWMP
Data Register
Freescale Semiconductor
M
U
X
To Pin
Driver