ST62T00CB6 STMicroelectronics, ST62T00CB6 Datasheet - Page 53

• Manufacturer Part Number: ST62T00CB6
• Description: IC MCU 8BIT OTP 1K 16-PDIP
• Manufacturer: STMicroelectronics
• Series: ST6r

Specifications of ST62T00CB6

• Core Processor: ST6
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, WDT
• Number Of I /o: 9
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Controller Family/series: ST6
• No. Of I/o's: 9
• Ram Memory Size: 64Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: ST62T0x
• Core: ST6
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 9
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Cpu Family: ST6
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 64Byte
• # I/os (max): 9
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 16
• Package Type: PDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-2093-5

9.3 INSTRUCTION SET
The ST6 offers a set of 40 basic instructions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di-
vided into six different types: load/store, arithme-
tic/logic, conditional branch, control instructions,
jump/call, and bit manipulation. The following par-
agraphs describe the different types.
All the instructions belonging to a given type are
presented in individual tables.
Table 15. Load & Store Instructions
Legend:
X, Y Index Registers,
V, W Short Direct Registers
#
rr
*
LD A, X
LD A, Y
LD A, V
LD A, W
LD X, A
LD Y, A
LD V, A
LD W, A
LD A, rr
LD rr, A
LD A, (X)
LD A, (Y)
LD (X), A
LD (Y), A
LDI A, #N
LDI rr, #N
Immediate data (stored in ROM memory)
Data space register
Affected
Not Affected
Instruction
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Direct
Direct
Indirect
Indirect
Indirect
Indirect
Immediate
Immediate
Addressing Mode
Doc ID 4563 Rev 5
Load & Store. These instructions use one, two or
three bytes depending on the addressing mode.
For LOAD, one operand is the Accumulator and
the other operand is obtained from data memory
using one of the addressing modes.
For Load Immediate, one operand can be any of
the 256 data space bytes while the other is always
immediate data.
Bytes
1
1
1
1
1
1
1
1
2
2
1
1
1
1
2
3
ST6200C ST6201C ST6203C
Cycles
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Z
*
Flags
C
53/100
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1