MC908JB16JDWE Freescale Semiconductor, MC908JB16JDWE Datasheet - Page 301

• Manufacturer Part Number: MC908JB16JDWE
• Description: IC MCU 16K FLASH 6MHZ USB 20SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB16JDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SCI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C/SCI/SPI/USB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 2.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.5 COP Control Register
17.6 Interrupts
17.7 Monitor Mode
17.8 Low-Power Modes
MC68HC908JB16
Freescale Semiconductor
—
Rev. 1.1
Address:
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
The COP does not generate CPU interrupt requests.
When monitor mode is entered with V
disabled as long as V
monitor mode is entered by having blank reset vectors and not having
V
occurs.
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
Reset:
Read:
Write:
TST
on the IRQ pin, the COP is automatically disabled until a POR
$FFFF
Computer Operating Properly (COP)
Bit 7
Figure 17-3. COP Control Register (COPCTL)
6
TST
remains on the IRQ pin or the RST pin. When
5
Clears COP counter (any value)
Low byte of reset vector
Unaffected by reset
4
TST
Computer Operating Properly (COP)
on the IRQ pin, the COP is
3
2
1
Technical Data
Bit 0
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