HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 108

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

4.2.6
The RTE instruction is used to return from exception handling. When RTE is executed, the SPC
value is set in the PC, and the SSR value in SR, and the return from exception handling is
performed by branching to the SPC address.
If the SPC and SSR have been saved in external memory, set the BL bit in SR to 1, then restore
the SPC and SSR, and issue an RTE instruction.
4.3
There are three registers related to exception handling. These are peripheral module registers, and
therefore reside in area P4. They can be accessed by specifying the address in privileged mode
only.
1. The exception event register (EXPEVT) resides at address H'FFFFFFD4, and contains a 12-bit
2. The interrupt event register (INTEVT) resides at address H'FFFFFFD8, and contains a 12-bit
3. The TRAPA exception register (TRA) resides at address H'FFFFFFD0, and contains 8-bit
The bit configurations of the EXPEVT, INTEVT, and TRA registers are shown in figure 4.3.
88
imm:
exception code. The exception code set in EXPEVT is that for a reset or general exception
event. The exception code is set automatically by hardware when an exception occurs.
EXPEVT can also be modified by software.
exception code. The exception code set in EXPEVT is that for an interrupt request. The
exception code is set automatically by hardware when an exception occurs. INTEVT can also
be modified by software.
immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when
a TRAPA instruction is executed. TRA can also be modified by software.
EXPEVT register and INTEVT register
31
0
0: Reserved bits, always read as zero
8-bit immediate data in TRAPA instruction
Returning from Exception Handling
Register Description
Figure 4.3 Bit Configurations of EXPEVT, INTEVT, and TRA Registers
0 Exception code
11
0
TRA register
31
0
0
9
imm
2 0
00