HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 137

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

6.4
6.4.1
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt from the interrupt requests sent,
3. The priority level of the interrupt selected by the interrupt controller is compared with the
4. The CPU receives an interrupt at a break in instructions.
5. The interrupt source code is set in the interrupt event register (INTEVT).
6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively.
7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1.
8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the
Notes: 1. The interrupt mask bits (I3–I0) in the status register (SR) are not changed by
following the priority levels set in interrupt priority registers A and B (IPRA and IPRB).
Lower priority interrupts are held pending. If two of these interrupts have the same priority
level or if multiple interrupts occur within a single module, the interrupt with the highest
default priority or the highest priority within its IPR setting unit (as indicated in table 6.4) is
selected.
interrupt mask bits (I3–I0) in the status register (SR) of the CPU. If the request priority level is
higher than the level in bits I3–I0, the interrupt controller accepts the interrupt and sends an
interrupt request signal to the CPU. When the interrupt controller receives an interrupt, a low
level is output from the IRQOUT pin.
vector base register (VBR) and H'00000600). The interrupt handler may branch with the
INTEVT register value as its offset in order to identify the interrupt source. This enables it to
branch to the handling routine for the individual interrupt source.
2. IRQOUT outputs a low level until the interrupt request is cleared. However, if the
3. The interrupt source flag should be cleared in the interrupt handler. To ensure that an
INTC Operation
Interrupt Sequence
acceptance of an interrupt in the SH7708 Series.
interrupt source is masked by an interrupt mask bit, the IRQOUT pin returns to the
high level. The level is output without regard to the BL bit.
interrupt request that should have been cleared is not inadvertently accepted again, read
the interrupt source flag after it has been cleared, then wait for the interval shown in
table 6.6 (Time for priority decision and SR mask bit comparison) before clearing the
BL bit or executing an RTE instruction.
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