HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 243

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

10.3
10.3.1
The SH7708 Seires supports both big-endian mode, in which the 0 address is the most significant
byte in the byte data, and little-endian mode, in which the 0 address is the least significant byte.
Switching between the two is designated by an external pin (MD5 pin) at the time of a power-on
reset. After a power-on reset, big-endian mode is set when MD5 is low, and little-endian mode is
set when MD5 is high.
Three data bus widths are available for normal memory (byte, word, longword) and two data bus
widths (word and longword) for DRAM and pseudo-SRAM. Only longword is available for
synchronous DRAM. For the PCMCIA interface, choose from byte and word. This means data
alignment is done by matching the device’s data width and endian. The access unit must also be
matched to the device’s bus width. This also means that when longword data is read from a byte-
width device, four read operations must be executed. In the SH7708 Series, data alignment and
conversion of data length is performed automatically between the respective interfaces.
Tables 10.6 through 10.11 show the relationship between endian, device data width, and access
unit.
Table 10.6 32-Bit External Device/Big Endian Access and Data Alignment
Operation
Address 0
byte access
Address 1
byte access
Address 2
byte access
Address 3
byte access
Address 0
word access
Address 2
word access
Address 0
longword
access
BSC Operation
Endian/Access Size and Data Alignment
D31–D24 D23–D16 D15–D8 D7–D0
Data
7–0
—
—
—
Data
15–8
—
Data
31–24
—
Data
7–0
—
—
Data
7–0
—
Data
23–16
Data Bus
—
—
Data
7–0
—
—
Data
15–8
Data
15–8
—
—
—
Data
7–0
—
Data
7–0
Data
7–0
WE3,
CASHH,
DQMUU
Asserted —
—
—
—
Asserted Asserted —
—
Asserted Asserted Asserted Asserted
WE2,
CASHL,
DQMUL
Asserted —
—
—
—
Strobe Signal
WE1,
CASLH,
DQMLU
—
Asserted —
—
Asserted Asserted
WE0,
CASLL,
DQMLL
—
—
Asserted
—
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