HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 78

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

3.2
There are five registers for MMU processing. These are all peripheral module registers, so they are
located in address space area P4 and can only be accessed from privileged mode by specifying the
address. These registers consist of:
1. The page table entry register high (PTEH) register residing at address H'FFFFFFF0, which
2. The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to
3. The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the
4. The TLB exception address register (TEA) register residing at address H'FFFFFFFC, which
5. The MMU control register (MMUCR) residing at address H'FFFFFFF0, which makes the
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consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the virtual
address at which the exception is generated in the case of an MMU exception or address error
exception. When the page size is 4 kbytes, the VPN is the upper 20 bits of the virtual address,
but in this case the upper 22 bits of the virtual address are set. The VPN can also be modified
by software. As the ASID, software sets the number of the currently executing process. The
VPN and ASID are recorded in the TLB by the LDTLB instruction.
store the physical page number and page management information to be recorded in the TLB
by the LDTLB instruction. The contents of this register are only modified in response to a
software command.
base address of the current page table. The hardware does not set any value in TTB
automatically. TTB is available to software for general purposes.
stores the virtual address corresponding to a TLB or address error exception. This value
remains valid until the next exception or interrupt.
MMU settings described in figure 3.3. Any program that modifies MMUCR should reside in
the P1 or P2 area.
Register Description