HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 216

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Shadow Space: Areas 0–6 are decoded by physical address bits A28–A26, which correspond to
areas 000 to 110. Address bits 31–29 are ignored. This means that the range of area 0 addresses,
for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address
space obtained by adding to it H'20000000
on-chip I/O space, is H'FC000000 to H'FFFFFFF. The address space H'1C000000 + H'20000000
n–H'1FFFFFFF + H'20000000 n (n = 0–6) corresponding to the area 7 shadow space is reserved,
so should not be used.
10.1.6
The SH7708 Series supports PCMCIA standard interface specifications in physical space areas 5
and 6.
The interface supported is basically the IC memory card interface and I/O card interface defined
by PCMCIA Specifications Version 4.2. In addition, burst access is supported to enable high-
speed access.
Physical space area 5 supports the IC memory card interface only; area 6 supports both the IC
memory card interface and the I/O card interface.
Table 10.4 PCMCIA Interface Characteristics
Item
Access
Data bus
Memory type
Memory capacity
I/O section capacity
Other
Note: * Dynamic I/O bus sizing is supported only in little-endian mode.
196
PCMCIA Support
Area 6: H'1A000000
Area 5: H'14000000
Area 5: H'16000000
Area 6: H'18000000
Characteristics
Random access + burst access (ROM page mode correspondence added)
8/16 bits
Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM
Maximum 32 Mbytes
Maximum 32 Mbytes
Supports dynamic I/O bus sizing* and access to PCMCIA interface from
both the address translation area and non-address translation area
Figure 10.4 PCMCIA Space Allocation
Common memory/Attribute memory
Common memory/Attribute memory
n (n = 1–6). The address range for area 7, which is
I/O space