HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 230

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

and pseudo-SRAM, specifies address multiplexing, and controls refresh. This enables direct
connection of DRAM, synchronous DRAM and pseudo-SRAM without external circuits.
MCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. Bits TPC1–TPC0, RCD1–RCD0, TRWL1–TRWL0, TRAS1–TRAS0, BE, SZ,
AMX1–AMX0, and EDOMODE are written to in the initialization after a power-on reset and are
not then modified again. When RFSH and RMODE are written to, write the same values to the
other bits. When using DRAM, pseudo-SRAM, and synchronous DRAM, do not access areas 2
and 3 until this register is initialized.
Bits 15 and 14—RAS Precharge Time (TPC1, TPC0): When DRAM interface is selected as
connected memory, the TPC bits set the minimum number of cycles until the next RAS assertion
after RAS negation. When synchronous DRAM interface is selected, they set the minimum
number of cycles until output of the next bank-active command after precharge. When pseudo-
SRAM interface is selected, they set the minimum number of cycles until the next CE assertion
after CE negation.
Bit 15: TPC1
0
1
210
Initial value:
Bit name:
Bit name:
R/W:
R/W:
Bit:
Bit:
Bit 14: TPC0
0
1
0
1
TPC1
R/W
15
—
0
7
0
R
TPC0
R/W
R/W
BE
14
0
6
0
Normally
1 cycle (Initial value)
2 cycles
3 cycles
4 cycles
RCD1
R/W
R/W
SZ
13
0
5
0
AMX1
RCD0
R/W
R/W
12
0
4
0
TRWL1
AMX0
Description
R/W
R/W
11
0
3
0
Immediately after Self-Refresh
2 cycles (Initial value)
5 cycles
8 cycles
11 cycles
TRWL0
RFSH
R/W
R/W
10
0
2
0
RMODE
TRAS1
R/W
R/W
9
0
1
0
TRAS0
MODE
EDO
R/W
R/W
8
0
0
0