ST7FLITEU05M6 STMicroelectronics, ST7FLITEU05M6 Datasheet - Page 29

• Manufacturer Part Number: ST7FLITEU05M6
• Description: MCU 8BIT SGL VOLT FLASH SO-8
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU05M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FUS-PRIMER, ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

ST7LITEU05 ST7LITEU09
6.3.4
Figure 11. CPU registers
1.
Condition code register (CC)
The 8-bit condition code register contains the interrupt mask and four flags representative of
the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
Reset value: 111x 1xxx
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H Half carry bit
Bit 3 = I Interrupt mask bit
X = undefined value
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during
an ADD or ADC instruction. It is reset by hardware during the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM
and JRNM instructions.
7
1
RESET VALUE = STACK HIGHER ADDRESS
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
15
15
RESET VALUE = 1
PCH
1
8
8 7
RESET VALUE = XXh
RESET VALUE = XXh
RESET VALUE = XXh
7
7
7
7
1
7
1 1 X 1 X X
1 1 H I
1
PCL
N Z
H
Read/write
0
0
0
0
X
0
0
C
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
I
N
Central processing unit
Z
C
0
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