ST7FLITEU05M6 STMicroelectronics, ST7FLITEU05M6 Datasheet - Page 85

• Manufacturer Part Number: ST7FLITEU05M6
• Description: MCU 8BIT SGL VOLT FLASH SO-8
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU05M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FUS-PRIMER, ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

ST7LITEU05 ST7LITEU09
Note:
Table 34.
A write to the ADCCSR register (with ADON set) aborts the current conversion, resets the
EOC bit and starts a new conversion.
ADC data register high (ADCDRH)
Reset value: 0000 0000 (00h)
ADC Control/data register Low (ADCDRL)
Reset Value: 0000 0000 (00h)
Bits 7:5 = Reserved. Forced by hardware to 0.
Bit 4 = Reserved. Forced by hardware to 0.
Bit 3 = SLOW Slow mode
Table 35.
Bit 2 = Reserved. Forced by hardware to 0.
D9
This bit is set and cleared by software. It is used together with the SPEED bit to
configure the ADC clock speed as shown on the table below.
7
0
7
Channel selection
Configuring the ADC clock speed
D8
0
Channel pin
AIN0
AIN1
AIN2
AIN3
AIN4
D7
0
f
f
f
CPU
CPU
f
ADC
CPU
/2
/4
D6
0
Read/write
Read only
SLOW
D5
CH2
0
0
0
0
1
D4
0
SLOW
0
0
1
On-chip peripherals
CH1
0
0
1
1
0
D3
D1
SPEED
CH0
0
1
x
D2
D0
0
1
0
1
0
0
0
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