ST7FLITEU05M3TR STMicroelectronics, ST7FLITEU05M3TR Datasheet - Page 23

• Manufacturer Part Number: ST7FLITEU05M3TR
• Description: IC MCU 8BIT 2K FLASH 8SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU05M3TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FUS-PRIMER, ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

ST7LITEU05 ST7LITEU09
5
5.1
5.2
5.3
5.3.1
Data EEPROM
Introduction
The electrically erasable programmable read only memory can be used as a non volatile
back-up for storing data. Using the EEPROM requires a basic access protocol described in
this chapter.
Main features
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Figure 7.
Memory access
The data EEPROM memory read/write access modes are controlled by the E2LAT bit of the
EEPROM Control/Status register (EECSR). The flowchart in
different memory access modes.
Read operation (E2LAT=0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR
register is cleared.
EECSR
Up to 32 bytes programmed in the same cycle
EEPROM mono-voltage (charge pump)
Chained erase and programming cycles
Internal control of the global programming cycle duration
Wait mode management
Readout protection
EEPROM block diagram
0
ADDRESS BUS
0
DECODER
ADDRESS
0
0
4
0
DECODER
0
4
4
ROW
E2LAT
E2PGM
128
MULTIPLEXER
DATA
(1 ROW = 32 x 8 BITS)
MEMORY MATRIX
HIGH VOLTAGE
Figure 8
DATA BUS
EEPROM
PUMP
DATA LATCHES
128
32 x 8 BITS
describes these
Data EEPROM
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