ST7FLITEU05M3TR STMicroelectronics, ST7FLITEU05M3TR Datasheet - Page 43

• Manufacturer Part Number: ST7FLITEU05M3TR
• Description: IC MCU 8BIT 2K FLASH 8SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU05M3TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FUS-PRIMER, ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

ST7LITEU05 ST7LITEU09
8.2
Caution:
8.3
Note:
External interrupts
External interrupt vectors can be loaded into the PC register if the corresponding external
interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the
Halt low power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt
register (if available).
An external interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies
to the ei source. In case of a NANDed source (as described in the I/O ports section), a low
level on an I/O pin, configured as input with interrupt, masks the interrupt request even in
case of rising-edge sensitivity.
Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
●
●
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by:
●
●
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
being enabled) will therefore be lost if the clear sequence is executed.
Figure 18. Interrupt processing flowchart
The I bit of the CC register is cleared.
The corresponding enable bit is set in the control register.
Writing “0” to the corresponding bit in the status register or
Access to the status register while the flag is set followed by a read or write of an
associated register.
FROM RESET
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
FETCH NEXT INSTRUCTION
N
I BIT SET?
IRET?
Y
Y
N
LOAD PC FROM INTERRUPT VECTOR
N
STACK PC, X, A, CC
INTERRUPT
PENDING?
SET I BIT
Y
Interrupts
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