ST7FLITEU05M3TR STMicroelectronics, ST7FLITEU05M3TR Datasheet - Page 82

• Manufacturer Part Number: ST7FLITEU05M3TR
• Description: IC MCU 8BIT 2K FLASH 8SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU05M3TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FUS-PRIMER, ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

On-chip peripherals
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Conversion accuracy may therefore be impacted by voltage drops and noise in the event of
heavily loaded or badly decoupled power supply lines.
Figure 40. ADC block diagram
Digital A/D conversion result
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
If the input voltage (V
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (V
result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in the Electrical
Characteristics Section.
R
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the alloted time.
A/D conversion phases
The A/D conversion is based on two conversion phases:
1.
2.
AIN
Sample capacitor loading [duration: t
During this phase, the V
sample capacitor.
A/D conversion [duration: t
During this phase, the A/D conversion is computed (8 successive approximations
is the maximum recommended impedance for an analog input signal. If the impedance
AIN0
AIN1
AINx
f
CPU
ANALOG
AIN
AIN
DIV 2
MUX
) is greater than V
) is lower than V
EOC SPEED ADON
3
AIN
ADCDRH
0
1
HOLD
input voltage to be measured is loaded into the C
]
DIV 4
0
R
SS
ADCDRL
ADC
DD
(low-level voltage reference) then the conversion
SAMPLE
D9
0
(high-level voltage reference) then the
CH2
D8
SLOW
]
bit
1
0
CH1
D7
HOLD CONTROL
0
CH0
D6
0
f
C
ADC
D5
ADC
ADCCSR
0
D4
ST7LITEU05 ST7LITEU09
0
ANALOG TO DIGITAL
D3
SLOW
CONVERTER
D2
0
D1
D0
ADC