Z8F4823FT020SG Zilog, Z8F4823FT020SG Datasheet - Page 109

• Manufacturer Part Number: Z8F4823FT020SG
• Description: IC ENCORE MCU FLASH 48K 80QFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F4823FT020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z8F482x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4275; Z8F4823FT020SG

PS019921-0308
Watchdog Timer Reload Unlock Sequence
STOP mode. For more information on Stop Mode Recovery, see
Recovery
If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU
responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe-
cuting code from the vector address.
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the
device into the Reset state. The WDT status bit in the Watchdog Timer Control register is
set to 1. For more information on Reset, see
WDT Reset in STOP Mode
If enabled in STOP mode and configured to generate a Reset when a time-out occurs and
the device is in STOP mode, the Watchdog Timer initiates a Stop Mode Recovery. Both
the WDT status bit and the STOP bit in the Watchdog Timer Control register are set to 1
following WDT time-out in STOP mode. Default operation is for the WDT and its RC
oscillator to be enabled during STOP mode.
WDT RC Disable in STOP Mode
To minimize power consumption in STOP Mode, the WDT and its RC oscillator can be
disabled in STOP mode. The following sequence configures the WDT to be disabled when
the Z8 Encore! XP
STOP instruction:
1. Write 55H to the Watchdog Timer Control register (WDTCTL).
2. Write AAH to the Watchdog Timer Control register (WDTCTL).
3. Write 81H to the Watchdog Timer Control register (WDTCTL) to configure the WDT
This sequence only affects WDT operation in STOP mode.
Writing the unlock sequence to the Watchdog Timer (WDTCTL) Control register address
unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to
allow changes to the time-out period. These write operations to the WDTCTL register
address produce no effect on the bits in the WDTCTL register. The locking mechanism
prevents spurious writes to the Reload registers. Follow the steps below to unlock the
Watchdog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for write access.
1. Write
and its oscillator to be disabled during STOP Mode. Alternatively, write 00H to the
Watchdog Timer Control register (WDTCTL) as the third step in this sequence to
reconfigure the WDT and its oscillator to be enabled during STOP mode.
on page 45.
55H
to the Watchdog Timer Control register (WDTCTL).
®
F64XX Series devices enter STOP Mode following execution of a
Reset and Stop Mode Recovery
Z8 Encore! XP
Product Specification
Reset and Stop Mode
®
F64XX Series
Watchdog Timer
on page 45.
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