Z8F4823FT020SG Zilog, Z8F4823FT020SG Datasheet - Page 85

• Manufacturer Part Number: Z8F4823FT020SG
• Description: IC ENCORE MCU FLASH 48K 80QFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F4823FT020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z8F482x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4275; Z8F4823FT020SG

Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL)
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
IRQ1 Enable High and Low Bit Registers
T2ENL
7
T2ENL—Timer 2 Interrupt Request Enable Low Bit
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
I2CENL—I
SPIENL—SPI Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
The IRQ1 Enable High and Low Bit registers (see
a priority encoded enabling for interrupts in the Interrupt Request 1 register. Priority is
generated by setting bits in each register.
Table 30. IRQ1 Enable and Priority Encoding
Note: where x indicates the register bits from 0 through 7.
IRQ1ENH[x] IRQ1ENL[x]
0
0
1
1
T1ENL
6
2
C Interrupt Request Enable Low Bit
T0ENL
0
1
0
1
5
U0RENL
Disabled
Priority
Level 1
Level 2
Level 3
4
FC2H
R/W
Table 30
0
U0TENL
3
Description
Disabled
Nominal
Table 31
describes the priority control for IRQ1.
High
Low
Z8 Encore! XP
I2CENL
and
2
Table 32
Product Specification
SPIENL
1
®
on page 72) form
Interrupt Controller
F64XX Series
ADCENL
0
71