STR912FAW47X6 STMicroelectronics, STR912FAW47X6 Datasheet - Page 16

• Manufacturer Part Number: STR912FAW47X6
• Description: MCU ARM9 2048KB FLASH 128LQFP
• Manufacturer: STMicroelectronics
• Series: STR9r

Specifications of STR912FAW47X6

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: STR912x
• Core: ARM966E-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 96 KB
• Interface Type: CAN, I2C, IrDA, SSP, UART, USB
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: STR9
• Device Core: ARM966E-S
• Device Core Size: 16/32Bit
• Frequency (max): 96MHz
• Total Internal Ram Size: 96KB
• # I/os (max): 80
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2/3.6V
• Operating Supply Voltage (min): 1.65/1.77/2.5/2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: LQFP
• For Use With: MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-9039; STR912FAW47X6

Functional overview
3.7
3.7.1
3.7.2
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Non-volatile memories
There are two independent 32-bit wide burst Flash memories enabling true read-while-write
operation. The Flash memories are single-voltage erase/program with 20 year minimum
data retention and 100K minimum erase cycles. The primary Flash memory is much larger
than the secondary Flash.
Both Flash memories are blank when devices are shipped from ST. The CPU can boot only
from Flash memory (configurable selection of which Flash bank).
Flash memories are programmed half-word (16 bits) at a time, but are erased by sector or
by full array.
Primary Flash memory
Using the STR91xFA device configuration software tool and 3rd party Integrated Developer
Environments, it is possible to specify that the primary Flash memory is the default memory
from which the CPU boots at reset, or otherwise specify that the secondary Flash memory is
the default boot memory. This choice of boot memory is non-volatile and stored in a location
that can be programmed and changed only by JTAG In-System Programming. See
Section 6: Memory
The primary Flash memory has equal length 64K byte sectors. See
sectors per device type.
Table 3.
Secondary Flash memory
The smaller of the two Flash memories can be used to implement a bootloader, capable of
storing code to perform robust In-Application Programming (IAP) of the primary Flash
memory. The CPU executes code from the secondary Flash, while updating code in the
primary Flash memory. New code for the primary Flash memory can be downloaded over
any of the interfaces on the STR91xFA (USB, Ethernet, CAN, UART, etc.)
Additionally, the secondary Flash memory may also be used to store small data sets by
emulating EEPROM through firmware, eliminating the need for external EEPROM
memories. This raises the data security level because passcodes and other sensitive
information can be securely locked inside the STR91xFA device.
The secondary Flash memory is sectored as shown in
Both the primary Flash memory and the secondary Flash memory can be programmed with
code and/or data using the JTAG In-System Programming (ISP) channel, totally
independent of the CPU. This is excellent for iterative code development and for
manufacturing.
Size of primary Flash
Size of each sector
Number of sectors
Sectoring of primary Flash memory
mapping, for more detail.
Doc ID 13495 Rev 6
256 Kbytes
4
64 Kbytes
512 Kbytes
Table 4
8
according to device type.
Table 3
1 Mbyte
16
64 Kbytes
for number of
STR91xFAxxx
2 Mbytes
32