STR912FAW47X6 STMicroelectronics, STR912FAW47X6 Datasheet - Page 87

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STR912FAW47X6

Manufacturer Part Number
STR912FAW47X6
Description
MCU ARM9 2048KB FLASH 128LQFP
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet

Specifications of STR912FAW47X6

Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
STR912x
Core
ARM966E-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
96 KB
Interface Type
CAN, I2C, IrDA, SSP, UART, USB
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
80
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
STR9
Device Core
ARM966E-S
Device Core Size
16/32Bit
Frequency (max)
96MHz
Total Internal Ram Size
96KB
# I/os (max)
80
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2/3.6V
Operating Supply Voltage (min)
1.65/1.77/2.5/2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
LQFP
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-9039
STR912FAW47X6

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STR91xFAxxx
7.12.4
I
V
Table 45.
1. The maximum hold time of the START condition has only to be met if the interface does not stretch the low
2. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
3. C
2
DDQ
Symbol
C electrical characteristics
t
t
t
t
t
SU:STO
HD:STA
HD:DAT
SU:STA
SU:DAT
t
period of SCL signal
undefined region of the falling edge of SCL.
t
t
HIGH
LOW
BUF
C
t
b
t
R
F
b
= total capacitance of one bus line in pF
= 2.7 - 3.6 V, V
Bus free time between a STOP
and START condition
Hold time START condition.
After this period, the first clock
pulse is generated
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated
START condition
Data hold time
Data setup time
Rise time of both SDA and SCL
signals
Fall time of both SDA and SCL
signals
Setup time for STOP condition
Capacitive load for each bus
line
I
2
C electrical characteristics
Parameter
DD
= 1.65 - 2 V, T
(2)
(1)
Doc ID 13495 Rev 6
A
= -40 / 85 °C unless otherwise specified.
Min
250
4.0
4.7
4.0
4.7
4.0
4.7
Standard I
0
1000
Max
300
400
2
C
20+0.1C
20+0.1C
Electrical characteristics
Min
100
0.6
1.3
0.6
1.3
0.6
0.6
(3)
(3)
0
Fast I
b
b
2
C
Max
300
300
400
Unit
pF
87/102
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs

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