STR912FAW47X6 STMicroelectronics, STR912FAW47X6 Datasheet - Page 25

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STR912FAW47X6

Manufacturer Part Number
STR912FAW47X6
Description
MCU ARM9 2048KB FLASH 128LQFP
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet

Specifications of STR912FAW47X6

Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
STR912x
Core
ARM966E-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
96 KB
Interface Type
CAN, I2C, IrDA, SSP, UART, USB
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
80
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
STR9
Device Core
ARM966E-S
Device Core Size
16/32Bit
Frequency (max)
96MHz
Total Internal Ram Size
96KB
# I/os (max)
80
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2/3.6V
Operating Supply Voltage (min)
1.65/1.77/2.5/2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
LQFP
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-9039
STR912FAW47X6

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STR91xFAxxx
3.12.2
3.13
Note:
3.13.1
Battery supply
An optional stand-by voltage from a battery or other source may be connected to pin VBATT
to retain the contents of SRAM in the event of a loss of the main digital supplies (V
V
VBATT pin when the voltage of V
battery supply, the LVD must be enabled.
The VBATT pin also supplies power to the RTC unit, allowing the RTC to function even when
the main digital supplies (V
it is possible to select whether or not to power from VBATT only the RTC unit, or power the
RTC unit and the SRAM when the STR91xFA device is powered off.
System supervisor
The STR91xFA monitors several system and environmental inputs and will generate a
global reset, a system reset, or an interrupt based on the nature of the input and
configurable settings. A global reset clears all functions on the STR91xFA, a system reset
will clear all but the Clock Control Unit (CCU) settings and the system status register. At any
time, firmware may reset individual on-chip peripherals. System supervisor inputs include:
GR: means the input causes Global Reset, SR: means the input causes System Reset
The CPU may read a status register after a reset event to determine if the reset was caused
by a watchdog timer timeout or a voltage supply drop out. This status register is cleared only
by a power up reset.
Supply voltage brownout
Each operating voltage source (V
Detect (LVD) circuitry. The LVD will generate an early warning interrupt to the CPU when
voltage sags on either V
applications because the system can perform an orderly shutdown before the batteries
become too weak. The voltage trip point to cause a brown out interrupt is typically 0.25V
above the LVD dropout thresholds that cause a reset.
CPU firmware may prevent all brown-out interrupts by writing to interrupt mask registers at
run-time.
DDQ)
GR: CPU voltage supply (V
GR: I/O voltage supply (V
GR: Power-Up condition
SR: Watchdog timer timeout
SR: External reset pin (RESET_INn)
SR: JTAG debug reset command
. The SRAM will automatically switch its supply from the internal V
DD
DD
or V
Doc ID 13495 Rev 6
and V
DDQ
DDQ
DD
DD
DD
) drop out or brown out
) drop out or brown out
voltage inputs. This is an advantage for battery powered
drops below the LVD threshold. In order to use the
DDQ
and V
) are switched off. By configuring the RTC register,
DDQ
) is monitored separately by the Low Voltage
Functional overview
DD
source to the
DD
25/102
and

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