STR912FAW47X6 STMicroelectronics, STR912FAW47X6 Datasheet - Page 9

• Manufacturer Part Number: STR912FAW47X6
• Description: MCU ARM9 2048KB FLASH 128LQFP
• Manufacturer: STMicroelectronics
• Series: STR9r

Specifications of STR912FAW47X6

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: STR912x
• Core: ARM966E-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 96 KB
• Interface Type: CAN, I2C, IrDA, SSP, UART, USB
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: STR9
• Device Core: ARM966E-S
• Device Core Size: 16/32Bit
• Frequency (max): 96MHz
• Total Internal Ram Size: 96KB
• # I/os (max): 80
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2/3.6V
• Operating Supply Voltage (min): 1.65/1.77/2.5/2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: LQFP
• For Use With: MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-9039; STR912FAW47X6

STR91xFAxxx
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STR91xFA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
JTAG chaining inside the STR91xFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EMI 16-bit multiplexed connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
EMI 8-bit multiplexed connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
EMI 8-bit non-multiplexed connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
STR91xFAM 80-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
STR91xFAW 128-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
STR91xFA memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
LVD reset delay case 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LVD reset delay case 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LVD reset delay case 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Sleep mode current vs temperature with LVD on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Non-mux write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Non-mux bus read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Mux write diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Mux read diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Page mode read diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Sync burst write diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Sync burst read diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
MII_RX_CLK and MII_TX_CLK timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
MDC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Ethernet MII management timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Ethernet MII transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Ethernet MII receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SPI slave timing diagram with CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SPI slave timing diagram with CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Device marking for revision G LQFP80 and LQFP128 packages. . . . . . . . . . . . . . . . . . . . 93
Device marking for revision G LFBGA144 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Device marking for revision H LQFP80 and LQFP128 packages. . . . . . . . . . . . . . . . . . . . 93
Device marking for revision H LFBGA144 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Device marking for revision A LQFP80 and LQFP128 packages . . . . . . . . . . . . . . . . . . . . 94
Device marking for revision A LFBGA144 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
80-pin low profile quad flat package (LQFP80) outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
128-pin low profile quad flat package (LQFP128) outline . . . . . . . . . . . . . . . . . . . . . . . . . . 96
144-ball low profile fine pitch ball grid array package (LFBGA144) outline . . . . . . . . . . . . 97
Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 98
Doc ID 13495 Rev 6
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