ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 122

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
Interrupt Register (EF02h/EE02h)
Table 28 : INTID values and Corresponding Interrupt Sources
Notes 1) Bit INTPND of the corresponding message object has to
Bit Timing Configuration
According to the CAN protocol specification, a bit
time is subdivided into four segments:
Sync segment, propagation time segment, phase
buffer segment 1 and phase buffer segment 2.
Figure 63 : Bit Timing Definition
122/186
15
INTID
INTID
(2+N)
Bit
00
01
02
be cleared to give messages with a lower priority the
possibility to update INTID or to reset INTID to 00h (idle
state).
2) A message interrupt code is only displayed, if there is no
other interrupt request with a higher priority.
14
Sync
Seg
Interrupt Idle: There is no interrupt request pending.
Status Change Interrupt: The CAN controller has updated (not necessarily changed) the status in the
Control Register. This can refer to a change of the error status of the CAN controller (EIE is set and BOFF
or EWRN change) or to a CAN transfer incident (SIE must be set), like reception or transmission of a
message (RXOK or TXOK is set) or the occurrence of a CAN bus error (LEC is updated). The CPU may
clear RXOK, TXOK, and LEC, however, writing to the status partition of the Control Register can never
generate or reset an interrupt. To update the INTID value the status partition of the Control Register must
be read.
Message 15 Interrupt: Bit INTPND in the Message Control Register of message object 15 (last message)
has been set.
The last message object has the highest interrupt priority of all message objects.
Message N Interrupt: Bit INTPND in the Message Control Register of message object ‘N’ has been set
(N = 1...14).
Interrupt Identifier
This number indicates the cause of the interrupt. When no interrupt is pending, the value will be “00”.
13
RESERVED
12
1) 2)
11
1 time quantum
TSeg1
10
1 bit time
9
Cause of the Interrupt
8
XReg
sample point
Function
Each segment is a multiple of the time quantum t q
with t q = ( BRP + 1 ) x 2 x t
The Synchronization Segment (Sync seg) is
always 1 t q long. The Propagation Time Segment
and the Phase Buffer Segment1 (combined to
Tseg1) defines the time before the sample point,
while Phase Buffer Segment2 (Tseg2) defines the
time after the sample point. The length of these
segments is programmable (except Sync-Seg).
Note
7
6
For exact definition of these segments
please refer to the CAN Specification.
TSeg2
5
4
INTID
transmit point
R
3
1)
XCLK
Reset Value: - - XXh
Sync
Seg
2
1
0