ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 137

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Exiting Power Down Mode
When Power Down mode is entered, the CPU and
peripheral clocks are frozen, and the oscillator
and PLL are stopped. Power Down mode can be
exited by either asserting RSTIN or one of the
enabled EXxIN pin (Fast External Interrupt).
RSTIN must be held low until the oscillator and
PLL have stabilized.
EXxIN inputs are normally sampled interrupt
inputs. However, the Power Down mode circuitry
uses them as level-sensitive inputs. An EXxIN (x =
7...0) Interrupt Enable bit (bit CCxIE in respective
CCxIC register) need not to be set to bring the
device out of Power Down mode. An external RC
circuit must be connected, as shown in the follow-
ing figure:
Figure 71 :
Powerdown Mode with External Interrup
Figure 72 : Simplified Powerdown Exit Circuitry
ST10F280
RPD
External RC Circuit on RPD Pin for Exiting
Enter
PowerDown
External
interrupt
reset
+
V
DD
R0
C0
220k
1 F Typical
V
DD
V
DD
t
1M
D Q
D Q
Q1
Q2
cd
cd
Typical
Q
Q
System clock
Stop pll
stop oscillator
To exit Power Down mode with external interrupt,
an EXxIN pin has to be asserted for at least 40 ns
(x = 7...0). This signal enables the internal oscilla-
tor and PLL circuitry, and also turns on the weak
pull-down (see following figure). The discharging
of the external capacitor provides a delay that
allows the oscillator and PLL circuits to stabilize
before the internal CPU and Peripheral clocks are
enabled. When the Vpp voltage drops below the
threshold voltage (about 2.5 V), the Schmitt trig-
ger clears Q2 flip-flop, thus enabling the CPU and
Peripheral clocks, and the device resumes code
execution.
If the Interrupt was enabled (bit CCxIE=’1’ in the
respective CCxIC register) before entering Power
Down mode, the device executes the interrupt ser-
vice routine, and then resumes execution after the
PWRDN intruction (see note below). If the inter-
rupt was disabled, the device executes the
instruction following PWRDN instruction, and the
Interrupt Request Flag (bit CCxIR in the respec-
tive CCxIC register) remains set until it is cleared
by software.
Note: Due to internal pipeline, the instruction that
follows the PWRDN intruction is executed
before the CPU performs a call of the
interrupt service routine when exiting
power-down mode.
CPU and Peripherals clocks
V
DD
Weak Pull-down
(~ 200 A)
Pull-up
RPD
ST10F280
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