ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 130

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
17.2 - Synchronous Reset (Warm Reset)
A synchronous reset is triggered when RSTIN pin
is pulled low while RPD pin is at high level. In
order to properly activate the internal reset logic of
the MCU, the RSTIN pin must be held low, at least,
during 4 TCL (2 periods of CPU clock). The I/O
pins are set to high impedance and RSTOUT pin is
driven low. After RSTIN level is detected, a short
duration of 12 TCL (approximately 6 periods of
CPU clock) elapes, during which pending internal
hold states are cancelled and the current internal
access cycle if any is completed. External bus
cycle is aborted. The internal pull-down of RSTIN
pin is activated if bit BDRSTEN of
register was previously set by software. This bit is
Figure 66 : Synchronous Warm Reset (Short low pulse on RSTIN)
Notes: 1. RSTIN assertion can be released there.
130/186
2. If during the reset condition (RSTIN low), V
asynchronous reset is then immediately entered.
3. RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(f
4) RSTIN pin is pulled low if bit BDRSTEN (bit 5 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after
reset.
CPU
CPU Clock
RSTIN
RPD
RSTOUT
ALE
PORT0
Internal
Reset
Signal
= f
XTAL
/ 2), else it is 4 CPU clock cycles (8 TCL).
4 TCL 12 TCL
min.
200 A Discharge
1
max.
Internally pulled low
Reset Configuration
SYSCON
RPD
Latching point of PORT0
for system start-up configuration
voltage drops below the threshold voltage (about 2.5V for 5V operation), the
1024 TCL
4
always cleared on power-on or after a reset
sequence.
Exit of synchronous reset state
The internal reset sequence starts for 1024 TCL
(512 periods of CPU clock) and RSTIN pin level is
sampled. The reset sequence is extended until
RSTIN level becomes high. Then, the MCU
restarts. The system configuration is latched from
PORT0 and ALE, RD and R/W pins are driven to
their inactive level. The MCU starts program
execution from memory location 00'0000h in code
segment 0. This starting location will typically
point to the general initialization routine. Timing of
synchronous reset sequence are summarized in
Figure 66 and Figure 67.
V
6 or 8 TCL
RPD
2
> 2.5V Asynchronous Reset not entered.
3
INST #1