MC9S08QG84CFFER Freescale Semiconductor, MC9S08QG84CFFER Datasheet - Page 263

• Manufacturer Part Number: MC9S08QG84CFFER
• Description: IC MCU 8BIT 8K FLASH 16-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG84CFFER

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-QFN
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 512 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Mounting Style: SMD/SMT
• Height: 1 mm
• Interface Type: I2C, SCI, SPI
• Length: 5 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Width: 5 mm
• For Use With: DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.4.3.7
This register can be read or written at any time.
Freescale Semiconductor
Reset
RWBEN
DBGEN
RWAEN
BRKEN
Field
ARM
RWA
RWB
TAG
W
7
6
5
4
3
2
1
0
R
DBGEN
Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
0 DBG disabled
1 DBG enabled
Arm Control — Controls whether the debugger is comparing and storing information in the FIFO. A write is used
to set this bit (and ARMF) and completion of a debug run automatically clears it. Any debug run can be manually
stopped by writing 0 to ARM or to DBGEN.
0 Debugger not armed
1 Debugger armed
Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If
BRKEN = 0, this bit has no meaning or effect.
0 CPU breaks requested as force type requests
1 CPU breaks requested as tag type requests
Break Enable — Controls whether a trigger event will generate a break request to the CPU. Trigger events can
cause information to be stored in the FIFO without generating a break request to the CPU. For an end trace, CPU
break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a
begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL does not affect the timing of
CPU break requests.
0 CPU break requests not enabled
1 Triggers cause a break request to the CPU
R/W Comparison Value for Comparator A — When RWAEN = 1, this bit determines whether a read or a write
access qualifies comparator A. When RWAEN = 0, RWA and the R/W signal do not affect comparator A.
0 Comparator A can only match on a write cycle
1 Comparator A can only match on a read cycle
Enable R/W for Comparator A — Controls whether the level of R/W is considered for a comparator A match.
0 R/W is not used in comparison A
1 R/W is used in comparison A
R/W Comparison Value for Comparator B — When RWBEN = 1, this bit determines whether a read or a write
access qualifies comparator B. When RWBEN = 0, RWB and the R/W signal do not affect comparator B.
0 Comparator B can match only on a write cycle
1 Comparator B can match only on a read cycle
Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match.
0 R/W is not used in comparison B
1 R/W is used in comparison B
0
7
Debug Control Register (DBGC)
ARM
0
6
Table 17-4. DBGC Register Field Descriptions
Figure 17-7. Debug Control Register (DBGC)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
TAG
0
5
BRKEN
0
4
Description
RWA
0
3
RWAEN
2
0
RWB
0
1
Development Support
RWBEN
0
0
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