MC908QL4MDTER Freescale Semiconductor, MC908QL4MDTER Datasheet - Page 130

• Manufacturer Part Number: MC908QL4MDTER
• Description: IC MCU 8BIT 4K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QL4MDTER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

System Integration Module (SIM)
13.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop mode, stopping the CPU
and peripherals. If OSCENINSTOP is set, BUSCLKX4 will remain running in STOP and can be used to
run the AWU. Stop recovery time is selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles
down to 32. This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do
not require long start-up times from stop mode.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period.
Figure 13-18
130
ADDRESS BUS
INTERRUPT
BUSCLKX4
ADDRESS BUS
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
shows the stop mode recovery time from interrupt or break
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
DATA BUS
CPUSTOP
R/W
Figure 13-18. Stop Mode Recovery from Interrupt
STOP ADDR
STOP +1
Figure 13-17. Stop Mode Entry Timing
PREVIOUS DATA
MC68HC908QL4 Data Sheet, Rev. 8
STOP ADDR + 1
STOP + 2
NOTE
NOTE
STOP RECOVERY PERIOD
NEXT OPCODE
Figure 13-17
STOP + 2
SAME
shows stop mode entry timing and
SP
SAME
SP – 1
SAME
SAME
Freescale Semiconductor
SP – 2
SP – 3