MC908QL4MDTER Freescale Semiconductor, MC908QL4MDTER Datasheet - Page 141

• Manufacturer Part Number: MC908QL4MDTER
• Description: IC MCU 8BIT 4K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QL4MDTER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.8.3 SLIC Status Register
SLIC status register (SLCS) contains bits used to monitor the status of the SLIC module.
SLCACT — SLIC Active (Oscillator Trim Blocking Semaphore)
INITACK — Initialization Mode Acknowledge
Freescale Semiconductor
SLCACT is used to indicate if it is safe to trim the oscillator based upon current SLIC activity in LIN
mode. This bit indicates that the SLIC module might be currently receiving a message header,
synchronization byte, ID byte, or sending or receiving data bytes. This bit is read-only.
INITACK indicates whether the SLIC module is in the reset mode as a result of writing INITREQ in
SLCC1. While in the reset state the SLIC module clocks are stopped. Clearing the INITREQ allows the
SLIC to proceed and enter SLIC run mode (if SLCE is set). The module will clear INITACK after the
module has left reset mode and the SLIC will seek the next LIN header. This bit is read-only.
1 = SLIC module activity (not safe to trim oscillator)
0 = SLIC module not active (safe to trim oscillator)
1 = SLIC module is in reset state
0 = Normal operation
SLCACT is automatically set to 1 if a falling edge is seen on the SLCRX pin and has
successfully been passed through the digital RX filter. This edge is the potential beginning of a
LIN message frame.
SLCACT is cleared by the SLIC module only upon assertion of the RX Message Buffer Full
Checksum OK (SLCSV = $10) or the TX Message Buffer Empty Checksum Transmitted
(SLCSV = $08) interrupt sources.
Reset:
Read:
Write:
To guarantee timing, the user must ensure that the SLIC clock used allows
the proper communications timing tolerances and therefore internal
oscillator circuits might not be appropriate for use with BTM mode.
SLCACT may not be clear during all idle times of the bus. For example, if
IMSG was used to ignore the data interrupts of an extended message
frame, SLCACT will remain set until another LIN message is received and
either the RX Message Buffer Full Checksum OK (SLCSV = $10) or the TX
Message Buffer Empty Checksum Transmitted (SLCSV = $08) interrupt
sources are asserted and cleared. When clear, SLCACT always indicates
times when the SLIC module is not active, but it is possible for the SLIC
module to be not active with SLCACT set. SLCACT has no meaning in BTM
mode.
SLCACT
Bit 7
0
= Unimplemented
Figure 14-6. SLIC Status Register (SLCS)
6
0
0
MC68HC908QL4 Data Sheet, Rev. 8
INITACK
5
1
NOTE
NOTE
0
4
0
3
0
0
2
0
0
1
0
0
SLCF
Bit 0
0
Registers
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