MC908QL4MDTER Freescale Semiconductor, MC908QL4MDTER Datasheet - Page 140

• Manufacturer Part Number: MC908QL4MDTER
• Description: IC MCU 8BIT 4K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QL4MDTER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Slave LIN Interface Controller (SLIC) Module
IMSG — SLIC Ignore Message Bit
SLCIE — SLIC Interrupt Enable
14.8.2 SLIC Control Register 2
SLIC control register 2 (SLCC2) contains bits used to control various features of the SLIC module.
SLCWCM — SLIC Wait Clock Mode
BTM — UART Byte Transfer Mode
SLCE — SLIC Module Enable
140
IMSG cannot be cleared by a write of 0, but is cleared automatically by the SLIC module after the next
BREAK/SYNC symbol pair is validated. After it is set, IMSG will not keep data from being written to the
receive data buffer, which means that the buffers cannot be assumed to contain known valid message
data until the next receive buffer full interrupt. IMSG must not be used in BTM mode.
This bit can only be written once out of reset state.
Byte transmit mode bypasses the normal LIN message framing and checksum monitoring and allows
the user to send and receive single bytes in a method similar to a half-duplex UART. When enabled,
this mode reads the bit time register (SLCBT) value and assumes this is the value corresponding to
the number of SLIC clock counts for one bit time to establish the desired UART bit rate. The user
software must initialize this register prior to sending or receiving data, based on the input clock
selection, prescaler stage choice, and desired bit rate.
BTM forces the data length in SLCDLC to one byte (DLC = 0x00) and disables the checksum circuitry
so that CHKMOD has no effect. Refer to
information about how to use this mode. BTM sets up the SLIC module to send and receive one byte
at a time, with 8-bit data, no parity, and one stop bit (8-N-1). This is the most commonly used setup for
UART communications and should work for most applications. This is fixed in the SLIC and is not
configurable.
1 = SLIC to ignore data field of message, SLIC interrupts are suppressed until the next message
0 = Normal operation
1 = SLIC interrupt sources are enabled
0 = SLIC interrupt sources are disabled
1 = SLIC clocks stop when the CPU is placed into wait mode
0 = SLIC clocks continue to run when the CPU is placed into wait mode so that the SLIC can receive
1 = UART byte transfer mode enabled
0 = UART byte transfer mode disabled
1 = SLIC module enabled
0 = SLIC module disabled
header arrives
messages and wakeup the CPU.
Reset:
Read:
Write:
Bit 7
0
0
Figure 14-5. SLIC Control Register 2 (SLCC2)
= Unimplemented
6
0
0
MC68HC908QL4 Data Sheet, Rev. 8
5
0
0
14.9.15 Byte Transfer Mode Operation
0
4
0
SLCWCM
3
0
BTM
2
0
1
0
0
Freescale Semiconductor
for more detailed
SLCE
Bit 0
0