S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 582

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

128 KByte Flash Module (S12XFTMR128K1V1)
19.3.2.13 Flash Reserved1 Register (FRSV1)
This Flash register is reserved for factory testing.
All bits in the FRSV1 register read 0 and are not writable.
19.3.2.14 Flash ECC Error Results Register (FECCR)
The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see
fault information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault.
All FECCR bits are readable but not writable.
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Offset Module Base + 0x000D
Offset Module Base + 0x000E
Offset Module Base + 0x000F
Reset
Reset
Reset
W
W
W
R
R
R
0
0
0
0
7
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 19-21. Flash ECC Error Results Low Register (FECCRLO)
Figure 19-20. Flash ECC Error Results High Register (FECCRHI)
0
0
0
0
6
6
6
Figure 19-19. Flash Reserved1 Register (FRSV1)
Section
S12XS Family Reference Manual, Rev. 1.11
0
0
0
0
5
5
5
19.3.2.4). Once ECC fault information has been stored, no other
0
0
0
0
4
4
4
ECCR[15:8]
ECCR[7:0]
0
0
0
0
3
3
3
0
0
0
0
2
2
2
Freescale Semiconductor
0
0
0
0
1
1
1
0
0
0
0
0
0
0