S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 99

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
2.3.37
Freescale Semiconductor
Address 0x0253
Read: Anytime.
Write: Anytime.
DDRM
DDRM
DDRM
DDRM
RDRM
Field
Field
Reset
7-6
5-2
7-0
1
0
W
R
Port M data direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Port M data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI0 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
Port M data direction—
This bit determines whether the associated pin is an input or output.
The enabled CAN0 or SCI1 forces the I/O state to be an output. In this case the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
Port M data direction—
This bit determines whether the associated pin is an input or output.
The enabled CAN0 or SCI1 forces the I/O state to be an input. In this case the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
Port M reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
RDRM7
Port M Reduced Drive Register (RDRM)
0
7
RDRM6
0
6
Figure 2-35. Port M Reduced Drive Register (RDRM)
Table 2-32. DDRM Register Field Descriptions
Table 2-33. RDRM Register Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
RDRM5
0
5
RDRM4
0
4
Description
Description
RDRM3
3
0
RDRM2
0
Port Integration Module (S12XSPIMV1)
2
RDRM1
Access: User read/write
0
1
RDRM0
0
0
99
1