S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 633

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

fault information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault.
All FECCR bits are readable but not writable.
Freescale Semiconductor
GADDR[22:16]
Offset Module Base + 0x000E
Offset Module Base + 0x000F
Reset
Reset
PAR[7:0]
Field
15:8
6–0
W
W
R
R
0
0
7
7
ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits,
allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00.
Global Address — The GADDR[22:16] field contains the upper seven bits of the global address having
caused the error.
ECCRIX[2:0]
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 20-21. Flash ECC Error Results Low Register (FECCRLO)
Figure 20-20. Flash ECC Error Results High Register (FECCRHI)
000
001
010
011
100
101
110
111
0
0
6
6
Table 20-26. FECCR Index=000 Bit Descriptions
S12XS Family Reference Manual, Rev. 1.11
Parity bits read from
Table 20-25. FECCR Index Settings
Flash block
Bits [15:8]
0
0
5
5
Not used, returns 0x0000 when read
Not used, returns 0x0000 when read
Data 1 [15:0] (P-Flash only)
Data 2 [15:0] (P-Flash only)
Data 3 [15:0] (P-Flash only)
FECCR Register Content
0
0
4
4
ECCR[15:8]
Global address [15:0]
ECCR[7:0]
Description
Data 0 [15:0]
Bit[7]
0
0
0
3
3
64 KByte Flash Module (S12XFTMR64K1V1)
Global address
0
0
2
2
Bits[6:0]
[22:16]
0
0
1
1
0
0
0
0
633