MC9S08GT60ACFBE Freescale Semiconductor, MC9S08GT60ACFBE Datasheet - Page 111

• Manufacturer Part Number: MC9S08GT60ACFBE
• Description: IC MCU 60K FLASH 4K RAM 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT60ACFBE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 36
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Processor Series: S08GT
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: M68EVB908GB60E, M68DEMO908GB60E
• Minimum Operating Temperature: - 40 C
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

7.3.3
FLL engaged internal (FEI) is entered when any of the following conditions occur:
In FLL engaged internal mode, the reference clock is derived from the internal reference clock
ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as
selected by the MFD bits.
7.3.3.1
FEI unlocked is a temporary state that is entered when FEI is entered and the count error (Δn) output from
the subtractor is greater than the maximum n
lock detector to detect the unlock condition.
The ICG will remain in this state while the count error (Δn) is greater than the maximum n
the minimum n
In this state the output clock signal ICGOUT frequency is given by f
7.3.3.2
FLL engaged internal locked is entered from FEI unlocked when the count error (Δn), which comes from
the subtractor, is less than n
required by the lock detector to detect the lock condition. The output clock signal ICGOUT frequency is
given by f
The update made is an average of the error measurements taken in the four previous comparisons.
7.3.4
FLL bypassed external (FBE) is entered when any of the following conditions occur:
In this state, the DCO and IRG are off and the reference clock is derived from the external reference clock,
ICGERCLK. The output clock signal ICGOUT frequency is given by f
source is used (REFS = 0), then the input frequency on the EXTAL pin can be anywhere in the range
0 MHz to 40 MHz. If a crystal or resonator is used (REFS = 1), then frequency range is either low for
RANGE = 0 or high for RANGE = 1.
7.3.5
The FLL engaged external (FEE) mode is entered when any of the following conditions occur:
Freescale Semiconductor
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CLKS bits are written to 01
The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01
From SCM when CLKS = 10 and ERCS is high
When CLKS = 10, ERCS = 1 upon entering off mode, and off is then exited
From FLL engaged external mode if a loss of DCO clock occurs and the external reference is still
valid (both LOCS = 1 and ERCS = 1)
CLKS = 11 and ERCS and DCOS are both high.
The DCO stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 11.
ICGDCLK
FLL Engaged, Internal Clock (FEI) Mode
FLL Bypassed, External Clock (FBE) Mode
FLL Engaged, External Clock (FEE) Mode
FLL Engaged Internal Unlocked
FLL Engaged Internal Locked
lock
, as required by the lock detector to detect the lock condition.
/ R. In FEI locked, the filter value is only updated once every four comparison cycles.
lock
(max) and greater than nlock (min) for a given number of samples, as
MC9S08GB60A Data Sheet, Rev. 2
unlock
or less than the minimum n
ICGDCLK
ICGERCLK
Internal Clock Generator (S08ICGV2)
unlock
/ R.
/ R. If an external clock
, as required by the
lock
or less than
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