HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet
HD64F3337YCP16
Specifications of HD64F3337YCP16
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HD64F3337YCP16 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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H8/3397 Series 8 H8/3337 Series Hardware Manual Renesas Single–Chip Microcomputer The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to ...
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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used ...
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The H8/3337 Series and H8/3397 Series is a high-performance single-chip microcomputer that integrates peripheral functions necessary for system configuration with an H8/300 CPU featuring a 32-bit internal architecture as its core. On-chip peripheral functions include ROM, RAM, four kinds of ...
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User's Manuals on the H8/3337 Series and H8/3397 Series: Manual Title H8/3337 Series and H8/3397 Series Hardware Manual H8/300 Series Programming Manual Users manuals for development tools: Manual Title C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual Simulator Debugger Users ...
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Specification) There are two versions of the H8/3337F with on-chip flash memory: a dual-power-supply version and a single-power-supply (S-mask) version. Points to be noted when using the H8/3337F single- power-supply S-mask model are given below. 1. Notes on Voltage ...
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Product Type Names and Markings Table 1 shows examples of product type names and markings for the H8/3337YF (dual-power- supply specification) and H8/3337SF (single-power-supply specification), and the differences in flash memory programming power supply. Table 1 Differences in H8/3337YF ...
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Differences in S-Mask Model Table 2 shows the differences between the H8/3337F (dual-power-supply specification) and H8/3337SF (single-power-supply specification). Table 2 Differences between H8/3337F and H8/3337F S-Mask Model Dual-Power-Supply Model: Item H8/3337F Program must be applied from off-chip ...
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Dual-Power-Supply Model: Item H8/3337F Programming mode timing RES Prewrite Required before erasing processing Programming Block corresponding to programming processing address must be set in EBR1/EBR2 registers before programming EBR register EBR1, EBR2 configuration Memory ...
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Dual-Power-Supply Model: Item H8/3337F MDCR — — — WSCR RAMS RAM0 CKDBL FLMCR1 7 6 — — FLMCR2 — EBR1 7 6 LB7 LB6 LB5 EBR2 SB7 SB6 SB5 ...
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Table 3 shows differences in the development environments of the H8/3337YF (dual-power- supply specification) and H8/3337SF (single-power-supply specification). Table 3 H8/3337YF and H8/3337F S-Mask Model Development Environments Dual-Power-Supply Model: Item H8/3337YF E6000 Emulator Hitachi emulator unit HS3008EPI60H User Hitachi cable ...
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List of Items Revised or Added for This Version Section Page Notes on S-Mask Model (Single-Power-Supply Specification) 1.1 Overview 1.3.1 Pin Arrangement 4.3.1 Overview 75 6.2.2 Oscillator Circuit 101 to 105 (H8/3337SF) ...
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Section Page Only) [Option] 13.4 Application Notes 309 15.6.6 Effect on Absolute 352 Accuracy 18.3.2 Notes on 371 Programming 21.1.7 Flash Memory 500 Operating Modes 501 502 21.2.3 Erase Block 507 Register 2 (EBR2) 21.3.1 Boot Mode 512 513 21.4 ...
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Section Page 22.3.5 Application Notes 546 23 Electrical 549 to 596 Characteristics 23.3 Absolute Maximum 573 Ratings (H8/3337SF Low- Voltage Version 23.4 Electrical 574 to 586 Characteristics (H8/3337SF Low-Voltage Version) B.2 Function 661 Item and FLSHE = ...
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Section 1 Overview ........................................................................................................... 1.1 Overview............................................................................................................................ 1.2 Block Diagram................................................................................................................... 1.3 Pin Assignments and Functions......................................................................................... 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions........................................................................................................ 12 Section 2 CPU ....................................................................................................................... 25 2.1 Overview............................................................................................................................ 25 2.1.1 Features ................................................................................................................ 25 2.1.2 Address Space ...................................................................................................... 26 2.1.3 ...
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Section 3 MCU Operating Modes and Address Space 3.1 Overview............................................................................................................................ 63 3.1.1 Mode Selection..................................................................................................... 63 3.1.2 Mode and System Control Registers ................................................................... 63 3.2 System Control Register (SYSCR).................................................................................... 64 3.3 Mode Control Register (MDCR) ....................................................................................... 66 3.4 Address Space Map ...
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Section 7 I/O Ports ............................................................................................................... 107 7.1 Overview............................................................................................................................ 107 7.2 Port 1.................................................................................................................................. 112 7.2.1 Overview .............................................................................................................. 112 7.2.2 Register Configuration and Descriptions ............................................................. 113 7.2.3 Pin Functions in Each Mode ................................................................................ 115 7.2.4 Input Pull-Up Transistors ..................................................................................... 117 7.3 Port ...
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Section 8 16-Bit Free-Running Timer 8.1 Overview............................................................................................................................ 157 8.1.1 Features ................................................................................................................ 157 8.1.2 Block Diagram...................................................................................................... 158 8.1.3 Input and Output Pins........................................................................................... 159 8.1.4 Register Configuration ......................................................................................... 160 8.2 Register Descriptions......................................................................................................... 161 8.2.1 Free-Running Counter (FRC)............................................................................... 161 8.2.2 Output Compare Registers ...
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Setting of Overflow Flag (OVF) .......................................................................... 205 9.4 Interrupts............................................................................................................................ 206 9.5 Sample Application ........................................................................................................... 206 9.6 Application Notes.............................................................................................................. 207 9.6.1 Contention between TCNT Write and Clear ....................................................... 207 9.6.2 Contention between TCNT Write and Increment ............................................... 208 9.6.3 Contention ...
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Switching between Watchdog Timer Mode and Interval Timer Mode................ 232 11.4.5 Detection of Program Runaway ........................................................................... 232 Section 12 Serial Communication Interface 12.1 Overview............................................................................................................................ 233 12.1.1 Features ................................................................................................................ 233 12.1.2 Block Diagram...................................................................................................... 234 12.1.3 Input and Output Pins........................................................................................... 235 ...
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Slave Transmit Operation..................................................................................... 300 13.3.5 Slave Receive Operation ...................................................................................... 302 13.3.6 IRIC Set Timing and SCL Control....................................................................... 303 13.3.7 Noise Canceler...................................................................................................... 304 13.3.8 Sample Flowcharts ............................................................................................... 305 13.4 Application Notes.............................................................................................................. 309 Section 14 Host Interface (H8/3337 Series Only) 14.1 ...
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Single Mode (SCAN = 0) ..................................................................................... 342 15.4.2 Scan Mode (SCAN = 1) ....................................................................................... 344 15.4.3 Input Sampling and A/D Conversion Time.......................................................... 346 15.4.4 External Trigger Input Timing ............................................................................. 347 15.5 Interrupts............................................................................................................................ 348 15.6 Useage Notes ..................................................................................................................... 348 15.6.1 ...
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Section 19 ROM (32-kbyte Dual-Power-Supply Flash Memory Version) 19.1 Flash Memory Overview ................................................................................................... 373 19.1.1 Flash Memory Operating Principle ...................................................................... 373 19.1.2 Mode Programming and Flash Memory Address Space...................................... 374 19.1.3 Features ................................................................................................................ 374 19.1.4 Block Diagram...................................................................................................... 375 19.1.5 Input/Output ...
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Erase Block Register 1 (EBR1)............................................................................ 438 20.2.3 Erase Block Register 2 (EBR2)............................................................................ 439 20.2.4 Wait-State Control Register (WSCR) .................................................................. 440 20.3 On-Board Programming Modes ........................................................................................ 443 20.3.1 Boot Mode............................................................................................................ 444 20.3.2 User Programming Mode ..................................................................................... 450 20.4 Programming and ...
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Erase Mode........................................................................................................... 519 21.4.4 Erase-Verify Mode ............................................................................................... 519 21.4.5 Protect Modes....................................................................................................... 521 21.4.6 Interrupt Handling during Flash Memory Programming and Erasing ................. 523 21.5 Flash Memory Writer Mode (H8/3337SF)........................................................................ 524 21.5.1 Writer Mode Setting ............................................................................................. 524 21.5.2 Socket Adapter ...
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Bus Timing ........................................................................................................... 587 23.5.2 Control Signal Timing.......................................................................................... 588 23.5.3 16-Bit Free-Running Timer Timing ..................................................................... 590 23.5.4 8-Bit Timer Timing .............................................................................................. 591 23.5.5 Pulse Width Modulation Timer Timing ............................................................... 592 23.5.6 Serial Communication Interface Timing.............................................................. 593 23.5.7 I/O Port ...
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Overview The H8/3337 Series and the H8/3397 Series of single-chip microcomputers feature an H8/300 CPU core and a complement of on-chip supporting modules implementing a variety of system functions. The H8/300 CPU is a high-speed processor with an architecture ...
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Table 1.1 Features Item Specification CPU Two-way general register configuration Eight 16-bit registers, or Sixteen 8-bit registers High-speed operation Maximum clock rate (ø clock): 16 MHz 12MHz MHz ...
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Item Specification Serial communication Asynchronous or synchronous mode (selectable) interface (SCI) Full duplex: can transmit and receive simultaneously (2 channels) On-chip baud rate generator bus interface Conforms to Philips I (1 channel) [option] Includes single master mode ...
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... H8/3397 H8/3336Y H8/3396 4 Part Number 5-V Version (16 MHz) 4-V Version (12 MHz) 3-V Version (10 MHz) HD64F3337YF16 HD64F3337YF16 HD64F3337YFLH16 HD64F3337YFLH16 HD64F3337YTF16 HD64F3337YTF16 HD64F3337YTFLH16 HD64F3337YTFLH16 HD64F3337YCP16 HD64F3337YCP16 HD64F3337SF16 HD64F3337SF16 HD64F3337STF16 HD64F3337STF16 HD6473337YF16 HD6473337YF16 HD6473337YTF16 HD6473337YTF16 HD6473337YCP16 HD6473337YCP16 HD6433337YF16 HD6433337YVF10 HD6433337YF12 HD6433397VF10 HD6433397F16 HD6433397F12 HD6433337YTF16 ...
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Item Specification Series lineup Product Name H8/3334Y F-ZTAT H8/3334Y ZTAT H8/3334Y H8/3394 Note: The I option. • In mask ROM versions, the Y in the part number becomes products in which this Part Number 5-V Version (16 ...
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Block Diagram Figure 1.1 (a) shows a block diagram of the H8/3337 Series. Figure 1.1 (b) shows a block diagram of the H8/3397 Series ...
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Pin Assignments and Functions 1.3.1 Pin Arrangement Figure 1.2 (a) shows the pin arrangement of the FP-80A and TFP-80C packages for the H8/3337 Series, and figure 1.2 (b) shows the packages for the H8/3397 Series. Figure 1.3 (a) shows ...
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HDB HDB ...
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Pin Functions Pin Assignments in Each Operating Mode: Table 1.2 (a) and table 1.2 (b) lists the assignments of the pins of the FP-80A, TFP-80, CP-84, and CG-84 packages in each operating mode. Table 1.2 (a) Pin Assignments for ...
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Pin No. Expanded Modes FP-80A, CP-84, TFP-80C CG-84 Mode /FTOA/ 1 KEYIN /FTIA/ 2 KEYIN /FTIB/ 3 KEYIN /FTIC/ 4 KEYIN ...
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Pin No. Expanded Modes FP-80A, CP-84, TFP-80C CG-84 Mode /TMO 4 1 HIRQ * /TMRI 5 HIRQ * / / ...
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Pin No. Expanded Modes FP-80A, CP-84, TFP-80C CG-84 Mode — / ...
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Table 1.2 (b) Pin Assignments for H8/3397 Series in Each Operating Mode Pin No. FP-80A, CP-84, TFP-80C CG- ...
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Pin No. FP-80A, CP-84, TFP-80C CG- — ...
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Pin No. FP-80A, CP-84, TFP-80C CG- ...
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Pin Functions: Table 1.3 gives a concise description of the function of each pin. Table 1.3 Pin Functions Type Symbol Power Clock XTAL EXTAL ø RES System control STBY Address bus ...
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Type Symbol WAIT Bus control NMI Interrupt signals IRQ to 0 IRQ 7 Operating control Pin No. FP-80A, CP-84, TFP-80C CG-84 I/O Name and Function Wait: Requests the CPU ...
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Type Symbol 16-bit free- FTOA running timer FTOB (FRT) FTCI FTIA to FTID 8-bit timer TMO 0 TMO 1 TMCI 0 TMCI 1 TMRI 0 TMRI 1 PWM timer Serial communi- TxD 0 cation interface TxD ...
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Type Symbol Host interface HDB to 0 (HIF) (H8/3337 HDB 7 Series only IOR IOW HIRQ 1 HIRQ 11 HIRQ 12 Keyboard control KEYIN to 0 KEYIN 7 ECS Host interface ...
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Type Symbol A/D and D converters AV SS Flash memory FV PP [H8/3334YF-ZTAT] [H8/3337YF-ZTAT bus interface SCL (option) (H8/3337 Series SDA only) I/O ports ...
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Type Symbol I/O ports Note: In this chip, except for the S-mask model (single-power-supply specification), the same pin is used ...
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Overview The H8/300 CPU is a fast central processing unit with eight 16-bit general registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high-speed operation. 2.1.1 Features The main features of the H8/300 CPU ...
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Address Space The H8/300 CPU supports an address space with a maximum size of 64 kbytes for program code and data combined. The memory map differs depending on the mode (mode 3). For details, see section ...
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Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data ...
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Bit 5—Half-Carry Flag (H): This flag is set to 1 when the ADD.B, ADDX.B, SUB.B, SUBX.B, NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared to 0 otherwise. Similarly set to ...
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Data Formats The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. Bit manipulation instructions operate on 1-bit data specified as bit ..., ...
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Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data Type Register No 1-bit data RnH 1-bit data RnL 7 Byte data RnH MSB ...
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Memory Data Formats Figure 2.4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded ...
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Addressing Modes 2.4.1 Addressing Mode The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes No. Addressing Mode (1) Register direct (2) Register indirect (3) Register indirect with displacement ...
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Register Indirect with Pre-Decrement—@–Rn The @–Rn mode is used with MOV instructions that store register contents to memory similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is ...
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Calculation of Effective Address Table 2.2 shows how the H8/300 calculates effective addresses in each addressing mode. Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B, ADDX.B, SUBX.B, CMP.B, AND.B, OR.B, and XOR.B instructions can also ...
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Table 2.2 Effective Address Calculation Addressing Mode and No. Instruction Format 1 Register direct regm regn 2 Register indirect, @ reg 3 Register indirect with displacement, @(d:16, ...
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Addressing Mode and No. Instruction Format 5 Absolute address @aa abs @aa: abs 6 Immediate #xx IMM #xx: IMM 7 PC-relative @(d:8, PC disp ...
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Addressing Mode and No. Instruction Format 8 Memory indirect, @@aa abs Legend: reg, regm, regn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address Effective Address Calculation H'00 ...
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Instruction Set The H8/300 CPU has 57 types of instructions, which are classified by function in table 2.3. Table 2.3 Instruction Classification Function Instructions Data transfer MOV, MOVTPE Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, ...
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The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next. Operation Notation Rd General register (destination) Rs General register (source) Rn General ...
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Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Instruction Size* MOV B/W MOVTPE B MOVFPE B PUSH W POP W Note: * Size: Operand size ...
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Legend: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 ...
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Arithmetic Operations Table 2.5 describes the arithmetic instructions. See figure 2.6 in section 2.5.4, Shift Operations, for their object codes. Table 2.5 Arithmetic Instructions Instruction Size* ADD B/W SUB ADDX B SUBX INC B DEC ADDS W SUBS DAA ...
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Logic Operations Table 2.6 describes the four instructions that perform logic operations. See figure 2.6 in section 2.5.4, Shift Operations, for their object codes. Table 2.6 Logic Operation Instructions Instruction Size* AND XOR B NOT B ...
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Legend: op: Operation field rm, rn: Register field IMM: Immediate data Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes ...
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Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Instruction Size* BSET B BCLR B BNOT B BTST B BAND B BIAND BOR B BIOR BXOR B Note: * ...
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Instruction Size* BIXOR B BLD B BILD BST B BIST Note: * Size: Operand size B: Byte Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read- modify-write instructions. They read a byte of data, modify one ...
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Before Execution of BCLR Instruction Input/output Input Input Pin state Low High DDR Execution of BCLR Instruction BCLR #0, @P4DDR After Execution of BCLR Instruction Input/output Output Output Pin ...
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Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 ...
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Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont IMM ...
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Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Bcc — JMP — JSR — BSR — RTS — 50 Function Branches if condition cc is true. ...
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Legend: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes 8 7 disp 8 ...
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System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Instruction Size* RTE — SLEEP — LDC B STC B ANDC B ORC B XORC B NOP ...
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Block Data Transfer Instruction Table 2.11 describes the EEPMOV instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction Instruction Size EEPMOV — 15 Legend: op: Operation field Figure 2.10 Block Data Transfer Instruction Function ...
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Notes on EEPMOV Instruction 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified the address specified by R6 R4L 2. ...
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CPU States 2.6.1 Overview The CPU has three states: the program execution state, exception-handling state, and power-down state. The power-down state is further divided into three modes: sleep mode, software standby mode, and hardware standby mode. Figure 2.11 summarizes ...
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Exception handling request Exception- handling state RES = 1 Reset state A transition to the reset state occurs when RES goes low, except when the chip Notes the hardware standby mode. A transition from any state to ...
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Power-Down State The power-down state includes three modes: sleep mode, software standby mode, and hardware standby mode. Sleep Mode: Is entered when a SLEEP instruction is executed. The CPU halts, but CPU register contents remain unchanged and the on-chip ...
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Internal address bus Internal read signal Internal data bus (read) Internal write signal Internal data bus (write) Figure 2.13 On-Chip Memory Access Cycle ø Address bus AS: High RD: High WR: High Data bus: High impedance state Figure 2.14 ...
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Access to On-Chip Supporting Modules and External Devices The on-chip supporting module registers and external devices are accessed in a cycle consisting of three states and T . Only one byte of data can be ...
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Address bus AS: High RD: High WR: High Data bus: High impedance state Figure 2.16 Pin States during On-Chip Supporting Module Access Cycle ø Address bus AS RD WR: High Data bus Figure 2.17 (a) External Device Access Timing ...
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T 1 ø Address bus AS RD: High WR Data bus Figure 2.17 (b) External Device Access Timing (Write) Write cycle state T state 2 Address Write data T state 3 61 ...
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Section 3 MCU Operating Modes and Address Space 3.1 Overview 3.1.1 Mode Selection The H8/3397 and H8/3337 Series operate in three modes numbered 1, 2, and 3. The mode is selected by the inputs at the mode pins (MD Table ...
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System Control Register (SYSCR) Bit 7 SSBY STS2 Initial value 0 Read/Write R/W The system control register (SYSCR 8-bit register that controls the operation of the chip. Bit 7—Software Standby (SSBY): Enables transition to the software standby ...
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F-ZTAT Version Bit 6: STS2 Bit 5: STS1 Note: When 1,024 states (STS2 to STS0 = 101) is selected, the following points should be noted period exceeding øp/1,024 (e.g. øp/2,048) is specified ...
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Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by a reset, but is not initialized in the software standby mode. Bit 0: RAME Description 0 The on-chip RAM is disabled. 1 The on-chip ...
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Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector table H'004B H'004C External address space H'F77F H'F780 On-chip RAM*, 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF Note: * External memory can be accessed at ...
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Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector table H'004B H'004C External address space H'F77F H'F780 2 On-chip RAM* , 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF Notes not access reserved ...
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Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector table H'004B H'004C External address space H'F77F H'F780 Reserved *1, *2 H'FB7F H'FB80 *2 On-chip RAM , 1,024 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF Notes: ...
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Section 4 Exception Handling 4.1 Overview The H8/3337 Series and H8/3397 Series recognize two kinds of exceptions: interrupts and the reset. Table 4.1 indicates their priority and the timing of their hardware exception-handling sequence. Table 4.1 Hardware Exception-Handling Sequences and ...
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The following sequence is carried out when reset exception handling begins. 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit in the condition code register (CCR) is set ...
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Figure 4.2 Reset Sequence (Mode 1) 73 ...
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Disabling of Interrupts after Reset After a reset interrupt were to be accepted before initialization of the stack pointer (SP: R7), the program counter and condition code register might not be saved correctly, leading to a program ...
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Table 4.2 Interrupts Interrupt source NMI IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 16-bit free-running ICIA (Input capture A) timer ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture ...
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Interrupt-Related Registers The interrupt-related registers are the system control register (SYSCR), IRQ sense control register (ISCR), IRQ enable register (IER), and keyboard matrix interrupt mask register (KMIMR). Table 4.3 Registers Read by Interrupt Controller Name System control register IRQ ...
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Bits 7 to 0—IRQ to IRQ Sense Control (IRQ7SC to IRQ0SC): These bits determine whether 7 0 IRQ to IRQ are level-sensed or sensed on the falling edge Bits IRQ7SC to IRQ0SC Description An interrupt ...
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Keyboard Matrix Interrupt Mask Register (KMIMR) KMIMR is provided as a register for keyboard matrix interrupt masking. This register controls interrupts from the KEYIN to KEYIN 7 Bits KMIMR7 to KMIMR0 of KMIMR correspond to key sense inputs KEYIN In ...
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KMIMR0 (1) P6 /KEYIN KMIMR6 (0) P6 /KEYIN /IRQ KMIMR7 (1) P6 /KEYIN 7 7 Initial values are given in parentheses Figure 4.3 KMIMR and IRQ IRQ ...
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External Interrupts The nine external interrupts are NMI and IRQ used to recover from software standby mode. NMI: A nonmaskable interrupt is generated on the rising or falling edge of the regardless of whether the I (interrupt mask) bit ...
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Interrupt Handling Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt requests, commands the CPU to start the hardware interrupt exception-handling sequence, and furnishes the necessary vector number. Figure 4.4 shows a block diagram of the ...
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When an NMI or another enabled interrupt is requested, the interrupt controller transfers the interrupt request to the CPU and indicates the corresponding vector number. (When two or more interrupts are requested, the interrupt controller selects the vector number of ...
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Program execution Interrupt requested? Yes NMI IRQ ? 0 Yes IRQ Latch vector no. Save PC Save CCR Reset I 1 Read vector address Branch to software interrupt-handling routine Figure 4.5 Hardware Interrupt-Handling Sequence No Yes ...
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SP – – – – (R7) Stack area Before interrupt is accepted PC : Upper byte of progam counter Lower byte of progam counter L CCR: Condition code register ...
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Interrupt accepted Interrupt priority decision. Wait for Instruction end of instruction. prefetch Interrupt request signal ø Internal address (1) bus Internal read signal Internal write signal Internal 16-bit (2) data bus (1) Instruction prefetch address (Pushed on stack. Instruction is ...
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Interrupt Response Time Table 4.4 indicates the number of states that elapse from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. Since on-chip memory is accessed 16 bits at a time, very ...
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Figure 4.8 shows an example in which the OCIAE bit is cleared to 0. ø Internal address bus Internal write signal OCIAE OCFA OCIA interrupt signal Figure 4.8 Contention between Interrupt and Disabling Instruction The above contention does not occur ...
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SP BSR instruction H'FECF set Upper byte of program counter Lower byte of program counter L R1L: General register SP: Stack pointer Figure 4.9 Example of Damage Caused by Setting an Odd Address ...
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Section 5 Wait-State Controller 5.1 Overview The H8/3337 Series and H8/3397 Series have an on-chip wait-state controller that enables insertion of wait states into bus cycles for interfacing to low-speed external devices. 5.1.1 Features Features of the wait-state controller are ...
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Input/Output Pins Table 5.1 summarizes the wait-state controller’s input pin. Table 5.1 Wait-State Controller Pins Name Abbreviation WAIT Wait 5.1.4 Register Configuration Table 5.2 summarizes the wait-state controller’s register. Table 5.2 Register Configuration Address Name H'FFC2 Wait-state control register ...
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Bit 7—RAM Select (RAMS) Bit 6—RAM Area Select (RAM0) Bits 7 and 6 select a RAM area for emulation of dual-power-supply flash memory updates. For details, see the flash memory description in section 19 and 20, ROM. Bit 5—Clock Double ...
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Wait Modes Programmable Wait Mode: The number of wait states (T inserted in all accesses to external addresses. Figure 5.2 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). ø Address bus AS ...
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Pin Wait Mode: In all accesses to external addresses, the number of wait states (T bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (ø) in the last of these ...
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Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (T WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (ø) in the ...
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Section 6 Clock Pulse Generator 6.1 Overview The H8/3337 Series and H8/3397 Series have a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a duty adjustment circuit, and a divider and a prescaler that generates clock signals for ...
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Wait-State Control Register (WSCR) WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals supplied to the supporting modules. It also controls wait state controller wait settings, RAM area setting for dual-power-supply flash memory, and ...
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Oscillator Circuit 6.2.1 Oscillator (Generic Device external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit generates a system clock signal. Alternatively, an external clock signal can be applied to the EXTAL pin. ...
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XTAL Figure 6.3 Equivalent Circuit of External Crystal Table 6.2 External Crystal Parameters Frequency (MHz max ( ) 500 C (pF max 0 Use a crystal with the same frequency as the desired system clock frequency ...
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Input of External Clock Signal Circuit Configuration: An external clock signal can be input as shown in the examples in figure 6.5. In example (b) in figure 6.5, the external clock signal should be kept high during standby. If the ...
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External Clock Input: The external clock signal should have the same frequency as the desired system clock (ø). Clock timing parameters are given in table 6.3 and figure 6.6. Table 6.3 Clock Timing V 5.5 V Item Symbol Min Low ...
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Table 6.4 External Clock Output Settling Delay Time Conditions 2 Item External clock output settling delay time Note includes DEXT cyc V 2 STBY IH ...
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EXTAL XTAL Figure 6.8 Connection of Crystal Oscillator (Example) Table 6.5 Damping Resistance Frequency (MHz) Rd max ( ) Crystal Oscillator: Figure 6.9 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in ...
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Not allowed Figure 6.10 Notes on Board Design around External Crystal Input of External Clock Signal Circuit Configuration: An external clock signal can be input as shown in the examples in figure 6.11. In example (b) ...
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External Clock Input: The external clock signal should have the same frequency as the desired system clock (ø). Clock timing parameters are given in table 6.7 and figure 6.12. Table 6.7 Clock Timing Item Low pulse width of external clock ...
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Table 6.8 External Clock Output Stabilization Delay Time Conditions 3 Item External clock output stabilization delay time Note includes DEXT cyc V 3 STBY IH ...
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106 ...
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Overview The H8/3337 Series and H8/3397 Series have six 8-bit input/output ports, one 7-bit input/output port, and one 3-bit input/output port, and one 8-bit dedicated input port. Table 7.1 lists the functions of each port in each operating mode. ...
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Table 7.1 (a) Port Functions for H8/3337 Series Port Description Pins Port 1 8-bit I/O port P1 Can drive LEDs Built-in input pull-ups Port 2 8-bit I/O port P2 Can drive LEDs Built-in input pull-ups Port 3 8-bit I/O port ...
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Port Description Pins Port 7 8-bit input port Port 8 7-bit I/O port P8 Bus buffer drive P8 capability ( Port 9 8-bit I/O port P9 Bus buffer drive ...
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Table 7.1 (b) Port Functions for H8/3397 Series Port Description Pins Port 1 8-bit I/O port P1 Can drive LEDs Built-in input pull- ups Port 2 8-bit I/O port P2 Can drive LEDs Built-in input pull-ups Port 3 8-bit I/O ...
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Port Description Pins Port 8 7-bit I/O port Port 9 8-bit I/O port Mode 1 /IRQ /SCK Serial communication interface 1 input/output (TxD 6 5 ...
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Port 1 7.2.1 Overview Port 8-bit input/output port with the pin configuration shown in figure 7.1. The pin functions differ depending on the operating mode. Port 1 has built-in, software-controllable MOS input pull-up transistors that can ...
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Register Configuration and Descriptions Table 7.2 summarizes the port 1 registers. Table 7.2 Port 1 Registers Name Port 1 data direction register Port 1 data register Port 1 input pull-up control register Port 1 Data Direction Register (P1DDR) Bit ...
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Port 1 Data Register (P1DR) Bit Initial value 0 Read/Write R/W P1DR is an 8-bit register that stores data for pins read, the value in P1DR is obtained directly, regardless of the actual pin ...
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Pin Functions in Each Mode Port 1 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 1 ...
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Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 1 can provide lower address output pins and general input pins. Each pin becomes a lower address output pin if its P1DDR bit is set to 1, and ...
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Input Pull-Up Transistors Port 1 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode ...
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Port 2 7.3.1 Overview Port 8-bit input/output port with the pin configuration shown in figure 7.5. The pin functions differ depending on the operating mode. Port 2 has built-in, software-controllable MOS input pull-up transistors that can ...
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Register Configuration and Descriptions Table 7.4 summarizes the port 2 registers. Table 7.4 Port 2 Registers Name Port 2 data direction register Port 2 data register Port 2 input pull-up control register Port 2 Data Direction Register (P2DDR) Bit ...
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Port 2 Data Register (P2DR) Bit Initial value 0 Read/Write R/W P2DR is an 8-bit register that stores data for pins read, the value in P2DR is obtained directly, regardless of the actual pin ...
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Pin Functions in Each Mode Port 2 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 2 ...
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Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 2 can provide upper address output pins and general input pins. Each pin becomes an upper address output pin if its P2DDR bit is set to 1, and ...
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Input Pull-Up Transistors Port 2 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode ...
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Port 3 pins Port Note: * The HDB to HDB 7 0 does not support ...
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Register Configuration and Descriptions Table 7.6 summarizes the port 3 registers. Table 7.6 Port 3 Registers Name Port 3 data direction register Port 3 data register Port 3 input pull-up control register Port 3 Data Direction Register (P3DDR) Bit ...
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Port 3 Data Register (P3DR) Bit Initial value 0 Read/Write R/W P3DR is an 8-bit register that stores data for pins read, the value in P3DR is obtained directly, regardless of the actual pin ...
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Pin Functions in Each Mode Port 3 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) ...
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Mode 3: In mode 3 (single-chip mode), when the host interface enable bit (HIE) is cleared the system control register (SYSCR), port general-purpose input/output port. A pin becomes an output pin when its P3DDR ...
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Input Pull-Up Transistors Port 3 has built-in programmable input pull-up transistors that are available in mode 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 3, set ...
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Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) Port 4 pins P4 (input/output)/ (input/output)/ (input/output)/TMRI 5 P4 (input/output)/TMO 4 Port 4 P4 (input/output)/TMCI 3 ...
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Register Configuration and Descriptions Table 7.8 summarizes the port 4 registers. Table 7.8 Port 4 Registers Name Port 4 data direction register Port 4 data register Port 4 Data Direction Register (P4DDR) Bit 7 P4 DDR P4 7 Initial ...
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Port 4 Data Register (P4DR) Bit Initial value 0 Read/Write R/W P4DR is an 8-bit register that stores data for pins read, the value in P4DR is obtained directly, regardless of the actual pin ...
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Pin Functions Port 4 has different pin functions depending on whether the chip not operating in slave mode. Table 7.9 indicates the pin functions of port 4. Table 7.9 Port 4 Pin Functions Pin Pin Functions ...
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Pin Pin Functions and Selection Method P4 /TMCI / Bit P4 DDR and the operating mode select the pin function as follows HIRQ * P4 DDR 11 3 Operating mode Pin function TMCI input is usable when ...
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Port 5 7.6.1 Overview Port 3-bit input/output port that is multiplexed with input/output pins (TxD serial communication interface 0. The port 5 pin functions are the same in all operating modes. Figure 7.13 shows the pin ...
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Port 5 Data Direction Register (P5DDR) Bit 7 — Initial value 1 Read/Write — P5DDR is an 8-bit register that controls the input/output direction of each pin in port 5. A pin functions as an output pin if the corresponding ...
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Pin Functions Port 5 has the same pin functions in each operating mode. All pins can also be used as SCI input/output pins. Table 7.11 indicates the pin functions of port 5. Table 7.11 Port 5 Pin Functions Pin ...
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Port 6 7.7.1 Overview Port 8-bit input/output port that is multiplexed with input/output pins (FTOA, FTOB, FTIA to FTID, FTCI) of the 16-bit free-running timer (FRT), with key-sense input pins, and with IRQ and IRQ input ...
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Port 6 Data Direction Register (P6DDR) Bit 7 P6 DDR P6 7 Initial value 0 Read/Write W P6DDR is an 8-bit readable/writable register that controls the input/output direction of each pin in port 6. A pin functions as an output ...
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Port 6 Input Pull-Up Control Register (KMPCR) Bit 7 KM PCR KM 7 Initial value 0 Read/Write R/W KMPCR is an 8-bit readable/writable register that controls the input pull-up transistors in port P6DDR bit is cleared to ...
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Pin Functions Port 6 has the same pin functions in all operating modes. The pins are multiplexed with FRT IRQ IRQ input/output, and 6 7 port 6. Table 7.13 Port 6 Pin Functions Pin Pin Functions and Selection Method ...
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Pin Pin Functions and Selection Method P6 /FTIB/ 3 KEYIN P6 DDR 3 3 Pin function P6 /FTIA/ 2 KEYIN P6 DDR 2 2 Pin function P6 /FTOA/ Bit OEA in TOCR of the FRT and bit P6 1 KEYIN ...
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Input Pull-Up Transistors Port 6 has built-in programmable input pull-up transistors. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up, set the corresponding KMPCR bit to 1 and clear the ...
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Port 7 7.8.1 Overview Port 8-bit input port that also provides the analog input pins for the A/D converter and analog output pins for the D/A converter. The pin functions are the same in all modes. ...
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Port 7 Input Data Register (P7PIN) Bit Initial value —* Read/Write R Note: * Depends on the levels of pins P77 to P70. When P7PIN is read, the pin states are always read. P7PIN is a read-only ...
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Port 8 pins P8 /SCK 6 P8 /RxD 5 P8 /TxD 4 Port 8 P8 /IOR /HA 0 Pin configuration in slave mode when STAC bit (input/output)/IRQ 6 IRQ ...
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Port 8 Data Direction Register (P8DDR) Bit 7 — P8 Initial value 1 Read/Write — P8DDR is an 8-bit readable/writable register that controls the input/output direction of each pin in port 8. A pin functions as an output pin if ...
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Pin Functions Pins are multiplexed with HIF input/output, SCI1 input/output and IRQ to IRQ input. Table 7.17 indicates the functions of pins Table 7.17 Port 8 Pin Functions Pin Pin ...
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Pin Pin Functions and Selection Method P8 /IRQ / Bit TE in SCR of SCI1, bit STAC in STCR, bit IOW*/TxD select the pin function as follows 1 Operating mode STAC TE P8 DDR 4 Pin function ...
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Pin Pin Functions and Selection Method P8 /HA * Bit P8 DDR and the operating mode select the pin function as follows Operating mode P8 DDR 0 Pin function Note: * H8/3337 Series only. H8/3397 Series ICs ...
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Port 9 7.10.1 Overview Port 8-bit input/output port that is multiplexed with interrupt input pins input/output pins for bus control signals (RD, WR, AS, WAIT), an input pin (ADTRG) for the A/D converter, an output pin ...
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Port 9 P9 /IRQ 1 P9 /IRQ 0 Note: *2 The EIOW and ECS does not support a host interface, and therefore does not have these pin functions. Figure 7.17 Port 9 Pin Configuration (cont) 7.10.2 Register Configuration and Descriptions ...
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Port 9 Data Direction Register (P9DDR) Bit 7 P9 DDR P9 7 Modes 1 and 2 Initial value 0 Read/Write W Mode 3 Initial value 0 Read/Write W P9DDR is an 8-bit readable/writable register that controls the input/output direction of ...
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Pin Functions Port 9 has one set of pin functions in modes 1 and 2, and a different set of pin functions in mode 3. The pins are multiplexed with IRQ input, system clock (ø) output, host interface input ...
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Pin Pin Functions and Selection Method P9 /RD Bit P9 DDR and the operating mode select the pin function as follows 3 3 Operating mode P9 DDR 3 Pin function P9 /IRQ DDR 2 Pin function IRQ ...
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156 ...
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Section 8 16-Bit Free-Running Timer 8.1 Overview The H8/3337 Series and H8/3397 Series have an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free-running counter as a time base. Applications of the FRT module include rectangular-wave output (up ...
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Block Diagram Figure 8.1 shows a block diagram of the free-running timer. Internal clock sources External clock source FTCI Clock select Compare- match A FTOA FTOB Control logic FTIA FTIB FTIC FTID Legend: OCRA, B: Output compare register A, ...
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Input and Output Pins Table 8.1 lists the input and output pins of the free-running timer module. Table 8.1 Input and Output Pins of Free-Running Timer Module Name Abbreviation Counter clock input FTCI Output compare A FTOA Output compare ...
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Register Configuration Table 8.2 lists the registers of the free-running timer module. Table 8.2 Register Configuration Name Timer interrupt enable register Timer control/status register Free-running counter (high) Free-running counter (low) Output compare register A/B (high) Output compare register A/B ...
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Register Descriptions 8.2.1 Free-Running Counter (FRC) Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRC is a 16-bit readable/writable up-counter that ...
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Input Capture Registers (ICRA to ICRD) Bit Initial value Read/Write There are four input capture registers each of which is a 16-bit read-only register. ...
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Similarly, when the BUFEB bit in TCR is set to 1, ICRD is used as a buffer register for ICRB. When input capture is buffered, if the two input edge bits are set to different values (IEDGA IEDGC or IEDGB ...
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Timer Interrupt Enable Register (TIER) Bit 7 ICIAE ICIBE Initial value 0 Read/Write R/W TIER is an 8-bit readable/writable register that enables and disables interrupts. TIER is initialized to H' reset and in the standby modes. Bit ...
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Bit 3—Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1. Bit 3: OCIAE Description 0 Output compare interrupt request A ...
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Timer Control/Status Register (TCSR) Bit 7 ICFA Initial value 0 Read/Write R/(W)* R/(W)* Note: * Software can write bits clear the flags, but cannot write these bits. TCSR is ...
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Bit 5—Input Capture Flag C (ICFC): This status bit is set flag input of a rising or falling edge of FTIC as selected by the IEDGC bit. When BUFEA = 0, this indicates capture of the FRC ...
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Bit 2—Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value matches the OCRB value. This flag must be cleared by software set by hardware, however, and cannot be set by software. ...