HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 296

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, after loading new data
Figure 12.6 shows an example of SCI transmit operation in asynchronous mode.
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the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
transmitting. If the TIE bit (TDR-empty interrupt enable) is set to 1 in SCR, the SCI requests a
TXI interrupt (TDR-empty interrupt) at this time.
Serial transmit data are transmitted in the following order from the TxD pin:
a. Start bit: One 0 bit is output.
b. Transmit data: Seven or eight bits are output, LSB first.
c. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor
d. Stop bit: One or two 1 bits (stop bits) are output.
e. Mark state: Output of 1 bits continues until the start bit of the next transmit data.
from TDR into TSR and transmitting the stop bit, the SCI begins serial transmission of the next
frame. If TDRE is 1, after setting the TEND bit to 1 in SSR and transmitting the stop bit, the
SCI continues 1-level output in the mark state, and if the TEIE bit (TSR-empty interrupt
enable) in SCR is set to 1, the SCI generates a TEI interrupt request (TSR-empty interrupt).
bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can
also be selected.