HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 26

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Rev.7.00 Oct. 10, 2008 Page xxiv of lxxxiv
REJ09B0366-0700
Item
14.3.2 DMA Transfer
Requests
14.3.4 Types of DMA
Transfer
Table 14.7
Relationship between
DMA Transfer Type,
Request Mode, and Bus
Mode
Table 14.8 External
Request Transfer
Sources and
Destinations in Normal
DMA Mode
14.3.5 Number of Bus
Cycle States and DREQ
Pin Sampling Timing
Page
569
582
583
585
Revision (See Manual for Details)
Description amended
The DS bit in CHCR0/CHCR1 is used to select either falling
edge detection or low level detection for the DREQ signal (level
detection when DS = 0, edge detection when DS = 1).
DREQ is accepted after a power-on reset if TE = 0, NMIF = 0,
and AE = 0, but transfer is not executed if DMA transfer is not
enabled (DE = 0 or DME = 0).
Notes amended
Notes: 2. Auto-request, or on-chip peripheral module request
Title ameded
Description added
DREQ Pin Sampling Timing: In external request mode, the
DREQ pin is sampled at the rising edge of CKIO clock pulses.
When DREQ input is detected, a DMAC bus cycle is generated
and DMA transfer executed after four CKIO cycles at the
earliest.
When falling edge detection is selected for DREQ, the DMAC
will recognize DREQ two cycles (CKIO) later because the
signal must pass through the asynchronous input
synchronization circuit. (There is a 1-cycle (CKIO) delay when
low-level detection is selected.)
The second and subsequent DREQ sampling operations are
performed one cycle after the start of the first DMAC transfer
bus cycle (in the case of single address mode).
possible. If the transfer request source is the SCI
(SCIF), either the transfer source must be SCRDR1
(SCFRDR2) or the transfer destination must be
SCTDR1 (SCFTDR2).