HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 889

MPU 3V 16K PB-FREE 208-QFP

HD6417750SF167V

Manufacturer Part Number
HD6417750SF167V
Description
MPU 3V 16K PB-FREE 208-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750SF167V

Core Processor
SH-4
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Manufacturer
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Part Number:
HD6417750SF167V
Manufacturer:
INTERSIL
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Part Number:
HD6417750SF167V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
18.1
This LSI has a 20-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port.
18.1.1
The features of the general-purpose I/O port are as follows:
• 20-bit I/O port with input/output direction independently specifiable for each bit
• Pull-up can be specified independently for each bit.
• Interrupt input is possible for 16 of the 20 I/O port bits.
• Use or non-use of the I/O port can be selected with the PORTEN bit in bus control register 2
The features of the SCI I/O port are as follows:
• Data can be output when the I/O port is designated for output and SCI enabling has not been
• The RxD pin value can be read at all times, allowing break state detection.
• SCK pin control is possible when the I/O port is designated for output and SCI enabling has
• The SCK pin value can be read at all times.
The features of the SCIF I/O port are as follows:
• Data can be output when the I/O port is designated for output and SCIF enabling has not been
• The RxD2 pin value can be read at all times, allowing break state detection.
• CTS2 and RTS2 pin control is possible when the I/O port is designated for output and SCIF
• The CTS2 and RTS2 pin values can be read at all times.
(BCR2).
set. This allows break function transmission.
not been set.
set. This allows break function transmission.
enabling has not been set.
Overview
Features
Section 18 I/O Ports
Rev.7.00 Oct. 10, 2008 Page 803 of 1074
Section 18 I/O Ports
REJ09B0366-0700

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