HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 802

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 15 Serial Communication Interface (SCI)
Rev.7.00 Oct. 10, 2008 Page 716 of 1074
REJ09B0366-0700
Note: When switching from transmit or receive operation to simultaneous transmit and receive
No
No
No
Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception
operations, first clear the TE bit and RE bit to 0, then set both these bits to 1.
to SCTDR1 and clear TDRE flag
Read receive data in SCRDR1,
Start of transmission/reception
End of transmission/reception
Read ORER flag in SCSSR1
Read RDRF flag in SCSSR1
Read TDRE flag in SCSSR1
Clear TE and RE bits
and clear RDRF flag
All data transferred?
Write transmit data
in SCSSR1 to 0
in SCSSR1 to 0
in SCRSR1 to 0
ORER = 1?
TDRE = 1?
RDRF = 1?
Yes
Yes
Yes
No
Error handling
Yes
1. SCI status check and transmit data
2. Receive error handling:
3. SCI status check and receive data
4. Serial transmission/reception
write:
Read SCSSR1 and check that the
TDRE flag is set to 1, then write
transmit data to SCTDR1 and clear
the TDRE flag to 0. Transition of the
TDRE flag from 0 to 1 can also be
identified by a TXI interrupt.
If a receive error occurs, read the
ORER flag in SCSSR1 , and after
performing the appropriate error
handling, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
read:
Read SCSSR1 and check that the
RDRF flag is set to 1, then read the
receive data in SCRDR1 and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
continuation procedure:
To continue serial transmission/
reception, finish reading the RDRF
flag, reading SCRDR1, and clearing
the RDRF flag to 0, before the MSB
(bit 7) of the current frame is received.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible, then write data to
SCTDR1 and clear the TDRE flag to
0.
(Checking and clearing of the TDRE
flag is automatic when the DMAC is
activated by a transmit-data-empty
interrupt (TXI) request, and data is
written to SCTDR1. Similarly, the
RDRF flag is cleared automatically
when the DMAC is activated by a
receive-data-full interrupt (RXI)
request and the SCRDR1 value is
read.)