SAK-XC888CLM-8FFA 5V AC Infineon Technologies, SAK-XC888CLM-8FFA 5V AC Datasheet - Page 93

• Manufacturer Part Number: SAK-XC888CLM-8FFA 5V AC
• Description: IC MCU 8BIT FLASH 64-LQFP
• Manufacturer: Infineon Technologies
• Series: XC8xxr

Specifications of SAK-XC888CLM-8FFA 5V AC

• Core Processor: XC800
• Core Size: 8-Bit
• Speed: 103.2MHz
• Connectivity: CAN, LIN, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.75K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFQFP
• Data Bus Width: 8 bit
• Data Ram Size: 1.75 KB
• Interface Type: UART, SSC
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: B158-H8743-X-X-7600IN - KIT STARTER XC886/888
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000210982

fractional divider) for generating a wide range of baud rates based on its input clock
see
Figure 30
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (
output of the prescaler (
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See
The baud rate (
•
•
•
•
Data Sheet
Input clock
Prescaling factor (2
Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional
divider mode)
8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
f
PCLK
Figure
Prescaler
30.
FDEN
FDM
Baud-rate Generator Circuitry
f
f
PCLK
f
BR
DIV
) value is dependent on the following parameters:
f
MOD
clk
) if the fractional divider is enabled (FDCON.FDEN = 1), or the
BRPRE
f
DIV
Fractional Divider
) if the fractional divider is disabled (FDEN = 0). For baud rate
Adder
) defined by bit field BRPRE in register BCON
FDRES
1
1
FDSTEP
0
f
MOD
‘0’
f
DIV
86
0
(overflow)
FDEN&FDM
10
11
01
00
10
00
01
11
R
0
1
Section
NDOV
Functional Description
8-Bit Baud Rate Timer
8-Bit Reload Value
3.14.
XC886/888CLM
V1.2, 2009-07
f
BR
f
PCLK
,