UPD78F0386GK-8EU-A Renesas Electronics America, UPD78F0386GK-8EU-A Datasheet - Page 364

• Manufacturer Part Number: UPD78F0386GK-8EU-A
• Description: MCU 96KB FLASH 5KB RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0/Lx2r

Specifications of UPD78F0386GK-8EU-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

362
(3) IIC flag register 0 (IICF0)
Condition for clearing (ACKD0 = 0)
Condition for clearing (STD0 = 0)
Condition for clearing (SPD0 = 0)
ACKD0
When a stop condition is detected
At the rising edge of the next byte’s first clock
Cleared by LREL0 = 1 (exit from communications)
When IICE0 changes from 1 to 0 (operation stop)
Reset
When a stop condition is detected
At the rising edge of the next byte’s first clock following
address transfer
Cleared by LREL0 = 1 (exit from communications)
When IICE0 changes from 1 to 0 (operation stop)
Reset
At the rising edge of the address transfer byte’s first
clock following setting of this bit and detection of a start
condition
When IICE0 changes from 1 to 0 (operation stop)
Reset
STD0
SPD0
Remark
This register sets the operation mode of I
IICF0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the STCF and IICBSY bits are read-
only.
The IICRSV bit can be used to enable/disable the communication reservation function (see 16.5.14
Communication reservation).
STCEN can be used to set the initial value of the IICBSY bit (see 16.5.15 Other cautions).
IICRSV and STCEN can be written only when the operation of I
register 0 (IICC0) = 0). When operation is enabled, the IICF0 register can be read.
Reset signal generation sets IICF0 to 00H.
0
1
0
1
0
1
Acknowledge was not detected.
Acknowledge was detected.
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect.
Stop condition was not detected.
Stop condition was detected. The master device’s communication is terminated and the bus is released.
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
Bit 7 of IIC control register 0 (IICC0)
Figure 16-6. Format of IIC Status Register 0 (IICS0) (3/3)
CHAPTER 16 SERIAL INTERFACE IIC0
User’s Manual U17504EJ2V0UD
2
C and indicates the status of the I
Detection of acknowledge (ACK)
Detection of start condition
Detection of stop condition
Condition for setting (ACKD0 = 1)
Condition for setting (STD0 = 1)
Condition for setting (SPD0 = 1)
After the SDA0 line is set to low level at the rising edge of
SCL0’s ninth clock
When a start condition is detected
When a stop condition is detected
2
C is disabled (bit 7 (IICE0) of IIC control
2
C bus.