UPD78F1142AF1-BA4-A Renesas Electronics America, UPD78F1142AF1-BA4-A Datasheet - Page 133

• Manufacturer Part Number: UPD78F1142AF1-BA4-A
• Description: MCU 16BIT 78K0R/KX3 64-FBGA
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1142AF1-BA4-A

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4) Port input mode registers (PIM0)
Address: F0040H
(5) Port output mode registers (POM0)
Address: F0050H
Symbol
Symbol
POM0
PIM0
This register sets the input buffer of P03 or P04 in 1-bit units.
TTL input buffer can be selected during serial communication with an external device of the different potential.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
This register sets the output mode of P02 to P04 in 1-bit units.
N-ch open drain output (V
device of the different potential, and for the SDA10 and SDA20 pins during simplified I
external device of the same potential.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
POMmn
PIM0n
0
1
0
1
7
0
7
0
Normal input buffer
TTL input buffer
Normal output mode
N-ch open-drain output (V
After reset: 00H
After reset: 00H
6
0
6
0
DD
Figure 4-31. Format of Port Input Mode Register
Figure 4-32. Format of Port Input Mode Register
tolerance) mode can be selected during serial communication with an external
R/W
R/W
5
0
5
0
DD
CHAPTER 4 PORT FUNCTIONS
tolerance) mode
User’s Manual U17854EJ9V0UD
POM04
PIM04
Pmn pin output mode selection
P0n pin input buffer selection
4
4
(n = 2 to 4)
(n = 3, 4)
POM03
PIM03
3
3
POM02
2
0
2
2
C communication with an
1
0
1
0
0
0
0
0
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