UPD78F1142AF1-BA4-A Renesas Electronics America, UPD78F1142AF1-BA4-A Datasheet - Page 830

• Manufacturer Part Number: UPD78F1142AF1-BA4-A
• Description: MCU 16BIT 78K0R/KX3 64-FBGA
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1142AF1-BA4-A

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

828
Port
functions
Clock
generator
Function
1-bit
manipulation
instruction for
port register n
(Pn)
CMC: Clock
operation mode
control register
CSC: Clock
operation status
control register
OSTC:
Oscillation
stabilization time
counter status
register
OSTS:
Oscillation
stabilization time
select register
Details of
Function
When a 1-bit manipulation instruction is executed on a port that provides both input
and output functions, the output latch value of an input port that is not subject to
manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from
input mode to output mode.
CMC can be written only once after reset release, by an 8-bit memory manipulation
instruction.
After reset release, set CMC before X1 or XT1 oscillation is started as set by the
clock operation status control register (CSC).
Be sure to set AMPH to 1 if the X1 clock oscillation frequency exceeds 10 MHz.
It is recommended to set the default value (00H) to CMC after reset release, even
when the register is used at the default value, in order to prevent malfunctioning
during a program loop.
After reset release, set the clock operation mode control register (CMC) before
starting X1 oscillation as set by MSTOP or XT1 oscillation as set by XTSTOP.
To start X1 oscillation as set by MSTOP, check the oscillation stabilization time of the
X1 clock by using the oscillation stabilization time counter status register (OSTC).
Do not stop the clock selected for the CPU/peripheral hardware clock (f
CSC register.
The setting of the flags of the register to stop clock oscillation (invalidate the external
clock input) and the condition before clock oscillation is to be stopped are as follows.
(See Table 5-2.)
After the above time has elapsed, the bits are set to 1 in order from MOST8 and
remain 1.
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than or equal to the count value which is to be checked by the OSTC register.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
• If the STOP mode is entered and then released while the internal high-speed
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS
register before executing the STOP instruction.
Setting the oscillation stabilization time to 20
To change the setting of the OSTS register, be sure to confirm that the counting
operation of the OSTC register has been completed.
Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
subsystem clock is being used as the CPU clock.
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
Cautions
μ
s or less is prohibited.
CLK
) with the
p.138
p.143
p.143
p.143
p.143
p.144
p.144
p.144
p.145
p.146
p.146
p.146
p.148
p.148
p.148
p.148
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