UPD78F1142AF1-BA4-A Renesas Electronics America, UPD78F1142AF1-BA4-A Datasheet - Page 242

• Manufacturer Part Number: UPD78F1142AF1-BA4-A
• Description: MCU 16BIT 78K0R/KX3 64-FBGA
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1142AF1-BA4-A

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.8 Operation of Plural Channels of Timer Array Unit
6.8.1 Operation as PWM function
(TS0n) is set to 1, INTTM0n is output.
synchronization with the count clock. When TCR0n = 0000H, INTTM0n is output. TCR0n loads the value of TDR0n
again. After that, it continues the similar operation.
the TO0m pin. TCR0m of the slave channel loads the value of TDR0m, using INTTM0n of the master channel as a
start trigger, and stops counting until the next start trigger (INTTM0n of the master channel) is input.
and inactive when TCR0m = 0000H.
240
Two channels can be used as a set to generate a pulse of any period and duty factor.
The period and duty factor of the output pulse can be calculated by the following expressions.
The master channel operates in the interval timer mode and counts the periods. When the channel start trigger
TCR0m of a slave channel operates in one-count mode, counts the duty factor, and outputs a PWM waveform from
The output level of TO0m becomes active one count clock after generation of INTTM0n from the master channel,
Caution To rewrite both TDR0n of the master channel and TDR0m of the slave channel, a write access is
Remark
Remark
Pulse period = {Set value of TDR0n (master) + 1} × Count clock period
Duty factor [%] = {Set value of TDR0m (slave)}/{Set value of TDR0n (master) + 1} × 100
0% output:
100% output: Set value of TDR0m (slave) ≥ {Set value of TDR0n (master) + 1}
necessary two times. The timing at which the values of TDR0n and TDR0m are loaded to TCR0n
and TRC0m is upon occurrence of INTTM0n of the master channel. Thus, when rewriting is
performed split before and after occurrence of INTTM0n of the master channel, the TO0m pin
cannot output the expected waveform. To rewrite both TDR0n of the master and TDR0m of the
slave, therefore, be sure to rewrite both the registers immediately after INTTM0n is generated
from the master channel.
n = 0, 2, 4
m = n + 1
The duty factor exceeds 100% if the set value of TDR0m (slave) > (set value of TDR0n (master) + 1),
it summarizes to 100% output.
Set value of TDR0m (slave) = 0000H
CHAPTER 6 TIMER ARRAY UNIT
TCR0n counts down starting from the loaded value of TDR0n, in
User’s Manual U17854EJ9V0UD